Archive for November, 2008

R6xx/R7xx Acceleration

Tuesday, November 18th, 2008

As most of you know, Matthias and I have been working on getting acceleration working on r6xx and r7xx radeon hardware.  We have a tool called r600_demo which basically sends command buffers to the drm.  We use r600_demo to build little tests to test different functionality (shaders, primitives, textures, etc.).  Now that the engine is pretty well understood, I’ve begun implementing EXA and Xv support and it’s coming along nicely (already useable).
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So when will all of this get released?  I can’t say exactly.  Soon I hope.  We are still caught up in the approval process.  There are several reasons why this has taken so long.  The approval process basically looks like this:
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1. Figure out what information we need to release
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This ended up taking longer than expected since the low level engine initialization stuff ended up being much more complex than we thought it would; as such we weren’t able to go through the rest of the hw information to find out what was needed and exactly how it all worked.  Once we got that working, it was much easier to get the rest figured out.  In addition, the r6xx programming model is radically different from the previous model (r3xx-r5xx) so we were not able to carry over as much existing knowledge.

2. Create proper documentation and code
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I had written an initial set of documentation earlier in the year based on initial hw design documentation, but a lot of it ended up changing before the hw actually got to silicon (features got dropped/added/changed/etc.).  It was only once we actually got the hw working that it became clear exactly which parts were accurate on the real hw.

3. Go through the IP review process
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This is the tough part.  It’s essentially a risk/benefit analysis of the various parts of the chip we want to release, where the risks are generally catastrophic, i.e., losing the ability to continue selling into certain other larger OS markets.  Couple that with the fact that many of the hw and sw architects that need to be involved in this are busy working on newer asics and you can see how this can take as long as it has.  Now that we have 1 and 2 mostly complete, 3 becomes a lot easier because we have much more precise information about what we want to release.  Whereas before it was “we want to release 3D specs,” now it’s “we want to release this information on these specific hw blocks.”  The good news is that we plan several asic generations ahead, so the current programming model stays pretty similar for several generations.  In addition, we are getting the necessary open source approval processes in place so this should happen much more quickly in the future.
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The initial release will likely be mostly code (r600_demo, EXA/Xv code, mesa driver, etc.) since that will be easier to initially get approval on, then followed up eventually by documentation.