Archive for June, 2009

radeon power management

Monday, June 1st, 2009

There have been a number of requests for information about the power management on radeon chips.  Most of the information is out there, it just hasn’t been taken advantage of it yet.  Here is a brief overview of the functionality and how to use it.  For more information about the atombios command and data tables see atombios.h.  Information on the pre-atom command and data tables is available in radeontool.

1. Engine clock scaling - Reducing the engine clock reduces power usage at the expense of performance.  Chips with atombios have a command table (SetEngineClock) to adjust the engine clock.  On pre-atom chips, I’ve provided a function to do this in xf86-video-ati (RADEONSetEngineClock() in radeon_pm.c).

2. Memory clock scaling - Reducing the memory clock reduces power usage at the expense of bandwidth.  When adjusting the memory clock you need to make sure you have enough bandwidth available to meet the needs of all current memory clients (displays, 2D engine, 3D, engine, overlays, etc.).  Chips with atombios have command tables (SetMemoryClock) to adjust the memory clock.  I have some code to do this on pre-atom chips, but you need execute oem specific memory reset and dll tables in the bios to properly initialize and reset the memory controller.  I haven’t sorted these out yet in clean way yet.

3. PCIE lane adjustment - Reducing the number of active PCIE lanes reduces power usage at the expense of bandwidth.  I’ve provided code in xf86-video-ati for changing the number of PCIE lanes on all PCIE capable asics (RADEONSetPCIELanes() in radeon_pm.c).

4. Voltage adjustment - Chips with atombios have command (SetVoltage) and data (PowerPlayInfo and IntegratedSystemInfo) tables regarding voltage control.  I haven’t had time to dig into how they work yet.  On pre-atom chips, the voltage is controlled via a gpio which is specified in the bios powerplay and integrated systems tables.  Voltage scaling is only available on chips that have a voltage regulator (oem dependent).

5. Clock Gating - Enabling clock gating allows the asic to dynamically turn off the clock to parts of the chip when they are not in use.  Chips with atombios have a command table (DynamicClockGating) to enable this. Support for pre-atom chips is in xf86-video-ati (LegacySetClockGating() in radeon_pm.c).

6. Pixel clock scaling on laptop LCD panels - Slower pixel clock programmed just like the normal pixel clock.  Tables (PowerPlayInfo in atombios and powerplay table in pre-atom) in the bios specify whether or not this is supported and what clock should be used.

7. Thermal sensors and fan control chips - Third party chips controlled by i2c.  The chips, i2c slave addresses, and gpio info for i2c are all specified in the bios data tables (PowerPlayInfo and GPIO_I2C_Info tables in atombios; powerplay and overdrive tables on pre-atom chips).  Documentation for most of the 3rd party chips are available from the manufacturer’s websites.

The current xf86-video-ati driver takes advantage of some of these options (engine clock scaling, pcie lanes, and clockgating) with my recent power management changes.  xf86-video-radeonhd as also picked up support for engine clock scaling.  However fully dynamic power management will need to be implemented in the new KMS (kernel modesetting) enabled drm since only that driver has the full view of the hardware necessary for fully dynamic state transitions (e.g., making sure power state is appropriate to support the requested rendering (2D, 3D, and video) and display operations (dual head vs. single head, etc.)).  Also, the drm can take advantage of existing i2c sensor drivers and infrastructure that are already part of the kernel for exposing things like temperature and fan control.