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Memory Controller

There are two views of vram, the GPU’s view and the CPU’s view. When I say CPU, that could be anything that’s running on your main processor: a device driver, a GL application, the xserver, a window manager. In most cases the CPU accesses vram via a PCI BAR (Base Address Register).

BARs are resources on PCI devices that are used for configuration and resource access. Video devices generally have at least two BARs, one for mapping MMIO register space, and one for mapping the framebuffer. Since the largest BAR size is 256 MB, this poses a problem for CPU access to vram beyond 256 MB. Vendors could add multiple BARS for access, but this would eat up a lot of address space.

Fortunately, the GPU does not have a problem accessing the full amount of vram as it has direct access to it via the built in memory controller. So while your new 512 MB card may only provide CPU access to 256 MB of vram, the gpu can use the other 256 MB to store things that the CPU doesn’t need ready access to.

The GPU has it’s own address space and it’s resources can be mapped into the address space however it likes. It can map vram to one block of addresses and GART memory (system memory) to another block. Internal GPU clients (CRTCs, overlays, 2D/3D engines, video decoders, etc.) access vram or gart space via the memory controller’s address space. So if you wanted to blit (copy) something from one location in vram to another, the 2D engine would use GPU addresses.

This entry was posted on Tuesday, January 29th, 2008 at 12:18 pm and is filed under xorg. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.