How Duoview works on S3 virge and savage. (what I've been able to figure 
out).

This is what I've been able to figure out with regard to duoview on S3 
chipsets.  I seem to be missing something important with regard to 
enabling crtc2.

There are two sets of CR timing regs.  They are paired and accessable via 
the same vga cr io space. access to the paired regs is controlled by sr26. 
Setting sr26 to 0x4f enables reads and writes on crtc2, 0x40 enables reads 
and writes on crtc1. the read and write bits are separate, so you can 
enable different combinations of reads and writes for copying regs or 
having crtc2 mirror crtc1.

There are two dot clocks that can be used with either crtc.

Relevant registers:

SR26
0: crtc1 read disable (reads from crtc2)
1: crtc1 read disable (reads from crtc2)
2: crtc2 write enable
3: crtc1 write disable

SR30
0: ?
1: ?
2: ?
3: crtc1 dot clock (0 - dclock1, 1 - dclock2)
4: crtc2 dot clock (0 - dclock1, 1 - dclock2)

SR31
0: 0
1: FP crtc (0 - crtc1, 1 - crtc2)
2: CRT crtc (0 - crtc1, 1 - crtc2)
3: 0
4: FP enable

3C2 - setting bits 2,3 to 11b enables dclock values from 
SR12/13/etc. rather than from the vga PLL regs.

SR12, SR13, SR29 - PLL values for dclock 1

SR0E, SR0F, SR29 - PLL values for dclock 2


Hardware cursors

CR45
0: enable cursor 1
2: enable cursor 2

CR46 - CR4F paired hw cursor bits (controlled by SR26).


Using the BIOS for duoview mode setting

1. set active devices

  ax=0x4f14
  bx=0x0003
  cx=display devices (0:crt, 1:lcd, 2:tv, 7:duoview)

for example,if you want CRT+LCD, you should set cx to 0x83 (bit 7 should be set)

2. set crtc1

refresh: 

  ax=0x4f14
  bx=0x0001
  cx=vesa mode
  di=refresh rate for crtc1

and mode:

  ax=0x4f02
  bx=vesa mode

3. set crtc2

  ax=0x4f14
  bx=0x8003
  cx=display devices (like above)
  dx=vesa mode
  di=refresh rate for crtc2