--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c.typo_fixes 2004-04-05 22:08:27.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2004-04-05 22:49:27.000000000 -0400 @@ -1503,7 +1503,7 @@ info->PanelXRes = RADEON_BIOS16(tmp+25); info->PanelYRes = RADEON_BIOS16(tmp+27); - xf86DrvMsg(0, X_INFO, "Panel Size from BIOS: %dx%d\n", + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel Size from BIOS: %dx%d\n", info->PanelXRes, info->PanelYRes); info->PanelPwrDly = RADEON_BIOS16(tmp+44); @@ -2843,7 +2843,7 @@ pScrn->virtualY = MAX(pScrn->virtualY, info->PanelYRes); xf86DrvMsg(pScrn->scrnIndex, X_INFO, - "No valid mode specified, force to native mdoe\n"); + "No valid mode specified, force to native mode\n"); } return new; @@ -5100,11 +5100,6 @@ | RADEON_PPLL_ATOMIC_UPDATE_EN | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); - xf86DrvMsg(0, X_INFO, "Wrote: rd=%d, fd=%d, pd=%d\n", - restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, - restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, - (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); - RADEONTRACE(("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", restore->ppll_ref_div, restore->ppll_div_3, @@ -6223,7 +6218,7 @@ save->fp2_gen_cntl = (RADEON_FP2_PANEL_FORMAT | RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - save->fp2_gen_cntl |= RADEON_FP2_DV0_EN; + save->fp2_gen_cntl |= RADEON_FP2_DVO_EN; } if (info->ChipFamily == CHIP_FAMILY_R200 || @@ -7081,9 +7076,9 @@ } else { CARD32 fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL); if (IsOn) { - fp2_gen_cntl |= RADEON_FP2_DV0_EN; + fp2_gen_cntl |= RADEON_FP2_DVO_EN; } else { - fp2_gen_cntl &= ~RADEON_FP2_DV0_EN; + fp2_gen_cntl &= ~RADEON_FP2_DVO_EN; } OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); } @@ -7179,7 +7174,7 @@ OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN); } } else if (info->DisplayType == MT_CRT) { RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); @@ -7190,7 +7185,7 @@ OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN); OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DV0_EN, ~RADEON_FP2_DV0_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN); } } else if (info->CloneType == MT_CRT) { RADEONDacPowerSet(pScrn, TRUE, !pRADEONEnt->ReversedDAC); @@ -7222,7 +7217,7 @@ OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN); } } else if (info->DisplayType == MT_CRT) { RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); @@ -7233,7 +7228,7 @@ OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN); OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON); if (info->ChipFamily >= CHIP_FAMILY_R200) { - OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DV0_EN); + OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN); } } else if (info->CloneType == MT_CRT) { RADEONDacPowerSet(pScrn, FALSE, !pRADEONEnt->ReversedDAC); --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h.typo_fixes 2004-04-04 18:42:43.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 2004-04-05 22:12:31.000000000 -0400 @@ -407,10 +407,10 @@ # define RADEON_DAC_PDWN_B (1 << 18) #define RADEON_TV_DAC_CNTL 0x088c # define RADEON_TV_DAC_STD_MASK 0x0300 +# define RADEON_TV_DAC_BGSLEEP (1 << 6) # define RADEON_TV_DAC_RDACPD (1 << 24) # define RADEON_TV_DAC_GDACPD (1 << 25) # define RADEON_TV_DAC_BDACPD (1 << 26) -# define RADEON_TV_DAC_BGSLEEP (1 << 26) #define RADEON_DISP_HW_DEBUG 0x0d14 # define RADEON_CRT2_DISP1_SEL (1 << 5) #define RADEON_DISP_OUTPUT_CNTL 0x0d64 @@ -653,8 +653,8 @@ # define RADEON_FP2_PAD_FLOP_EN (1 << 22) # define RADEON_FP2_CRC_EN (1 << 23) # define RADEON_FP2_CRC_READ_EN (1 << 24) -# define RADEON_FP2_DV0_EN (1 << 25) -# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26) +# define RADEON_FP2_DVO_EN (1 << 25) +# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 #define RADEON_FP_HORZ_STRETCH 0x028c --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c.typo_fixes 2004-04-05 22:17:47.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c 2004-04-05 22:26:58.000000000 -0400 @@ -133,12 +133,12 @@ { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, - { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600 (M10) NP (AGP)" }, + { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, - { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2 (M11) NV (AGP)" }, + { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" },