--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c.xrender 2004-05-20 10:03:39.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2004-05-25 01:12:44.000000000 -0400 @@ -133,6 +133,10 @@ { OPTION_REVERSE_DISPLAY,"ReverseDisplay", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_NOBIOS, "NoBIOS", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_REF_CLOCK, "RefClock", OPTV_INTEGER, {0}, FALSE }, +#ifdef RENDER + { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, +#endif { -1, NULL, OPTV_NONE, {0}, FALSE } }; @@ -1003,7 +1007,17 @@ info->IsIGP = FALSE; info->BusType = -1; info->HasSingleDAC = FALSE; + info->HasTCL = FALSE; switch (info->Chipset) { + case PCI_CHIP_RADEON_QD: + case PCI_CHIP_RADEON_QE: + case PCI_CHIP_RADEON_QF: + case PCI_CHIP_RADEON_QG: + info->ChipFamily = CHIP_FAMILY_RADEON; + info->HasTCL = TRUE; + info->HasCRTC2 = FALSE; + break; + case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: info->IsMobility = TRUE; @@ -1042,6 +1056,7 @@ case PCI_CHIP_R200_QL: case PCI_CHIP_R200_QM: info->ChipFamily = CHIP_FAMILY_R200; + info->HasTCL = TRUE; break; case PCI_CHIP_RADEON_LW: @@ -1050,6 +1065,7 @@ case PCI_CHIP_RV200_QW: /* RV200 desktop */ case PCI_CHIP_RV200_QX: info->ChipFamily = CHIP_FAMILY_RV200; + info->HasTCL = TRUE; break; case PCI_CHIP_RV250_Ld: @@ -1059,6 +1075,7 @@ case PCI_CHIP_RV250_If: case PCI_CHIP_RV250_Ig: info->ChipFamily = CHIP_FAMILY_RV250; + info->HasTCL = TRUE; break; case PCI_CHIP_RS300_5835: @@ -1079,6 +1096,7 @@ case PCI_CHIP_RV280_5962: case PCI_CHIP_RV280_5964: info->ChipFamily = CHIP_FAMILY_RV280; + info->HasTCL = TRUE; break; case PCI_CHIP_R300_AD: @@ -1090,6 +1108,7 @@ case PCI_CHIP_R300_NF: case PCI_CHIP_R300_NG: info->ChipFamily = CHIP_FAMILY_R300; + info->HasTCL = TRUE; break; case PCI_CHIP_RV350_NP: @@ -1106,6 +1125,7 @@ case PCI_CHIP_RV350_AT: case PCI_CHIP_RV350_AV: info->ChipFamily = CHIP_FAMILY_RV350; + info->HasTCL = TRUE; break; case PCI_CHIP_R350_AH: @@ -1117,6 +1137,7 @@ case PCI_CHIP_R350_NK: case PCI_CHIP_R360_NJ: info->ChipFamily = CHIP_FAMILY_R350; + info->HasTCL = TRUE; break; case PCI_CHIP_RV380_3150: @@ -1126,6 +1147,7 @@ case PCI_CHIP_RV380_3E54: info->ChipFamily = CHIP_FAMILY_RV380; info->BusType = BUS_TYPE_PCIE; + info->HasTCL = TRUE; break; case PCI_CHIP_RV370_5460: @@ -1136,6 +1158,7 @@ case PCI_CHIP_RV370_5B65: info->ChipFamily = CHIP_FAMILY_RV380; info->BusType = BUS_TYPE_PCIE; + info->HasTCL = TRUE; break; case PCI_CHIP_R420_JN: @@ -1148,6 +1171,7 @@ case PCI_CHIP_R420_JM: case PCI_CHIP_R420_JP: info->ChipFamily = CHIP_FAMILY_R420; + info->HasTCL = TRUE; break; case PCI_CHIP_R423_UH: @@ -1160,12 +1184,11 @@ case PCI_CHIP_R423_5D57: info->ChipFamily = CHIP_FAMILY_R420; info->BusType = BUS_TYPE_PCIE; + info->HasTCL = TRUE; break; default: - /* Original Radeon/7200 */ - info->ChipFamily = CHIP_FAMILY_RADEON; - info->HasCRTC2 = FALSE; + return FALSE; } /* Framebuffer */ @@ -2431,6 +2454,10 @@ } #endif +#ifdef RENDER + info->RenderAccel = xf86ReturnOptValBool (info->Options, OPTION_RENDER_ACCEL, FALSE); +#endif + return TRUE; } @@ -3002,6 +3029,12 @@ if (info->VideoTimerCallback) (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); + +#ifdef RENDER + if(info->RenderCallback) + (*info->RenderCallback)(pScrn); +#endif + } /* Called at the start of each server generation. */ @@ -3011,6 +3044,10 @@ RADEONInfoPtr info = RADEONPTR(pScrn); BoxRec MemBox; int y2; +#ifdef RENDER + int subPixelOrder = SubPixelUnknown; + char* s; +#endif RADEONTRACE(("RADEONScreenInit %x %d\n", pScrn->memPhysBase, pScrn->fbOffset)); @@ -3150,10 +3187,14 @@ fbPictureInit (pScreen, 0, 0); #ifdef RENDER - if (PictureGetSubpixelOrder (pScreen) == SubPixelUnknown) - { - int subPixelOrder; + if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { + if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; + else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; + else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; + PictureSetSubpixelOrder (pScreen, subPixelOrder); + } + if (PictureGetSubpixelOrder (pScreen) == SubPixelUnknown) { switch (info->DisplayType) { case MT_NONE: subPixelOrder = SubPixelUnknown; break; case MT_LCD: subPixelOrder = SubPixelHorizontalRGB; break; @@ -3464,6 +3505,9 @@ xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); } +#ifdef RENDER + if (info->RenderAccel) RADEONInit3DEngineForRender(pScrn); +#endif /* Colormap setup */ if (!miCreateDefColormap(pScreen)) return FALSE; if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, @@ -3570,7 +3614,6 @@ OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); - OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); /* we don't save/restore AGP_LOCATION here, it should be taken care of by kernel driver. Writing to @@ -3580,11 +3623,15 @@ */ OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->disp1_base_addr); - OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->disp2_base_addr); OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); OUTREG(RADEON_HOST_PATH_CNTL, restore->host_path_cntl); OUTREG(RADEON_DEFAULT_OFFSET, restore->default_offset); + if (info->HasCRTC2) { + OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->disp2_base_addr); + OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); + } + /* Workaround for the VT switching problem in dual-head mode. This * problem only occurs on RV style chips, typically when a FP and * CRT are connected. ???Do we still need this??? @@ -3662,7 +3709,7 @@ /* when there is only single head, we need to make sure * it's using first CRTC, no matter what type of display */ - if (!pRADEONEnt->Controller[1].IsUsed) { + if (!pRADEONEnt->Controller[1].IsUsed && info->HasCRTC2) { if ((info->ChipFamily != CHIP_FAMILY_RADEON) && (info->ChipFamily != CHIP_FAMILY_R200)) @@ -3722,7 +3769,6 @@ unsigned char *RADEONMMIO = info->MMIO; unsigned long tmp; - OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl); OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch); @@ -3906,7 +3952,7 @@ restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16)); - usleep(5000); /* Let the clock to lock */ + usleep(50000); /* Let the clock to lock */ OUTPLLP (pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_cntl, 0); } @@ -4366,7 +4412,7 @@ save->disp2_base_addr = 0; save->ov0_base_addr = 0; } - + info->fbLocation = (save->mc_fb_location & 0xffff) << 16; } static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary) @@ -5498,6 +5544,11 @@ } #endif + if(info->RenderTex) { + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + if (pScrn->vtSema) { RADEONRestore(pScrn); } --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c.xrender 2004-05-20 10:04:05.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accelfuncs.c 2004-05-20 12:01:37.000000000 -0400 @@ -1346,6 +1346,36 @@ | HARDWARE_PATTERN_SCREEN_ORIGIN | BIT_ORDER_IN_BYTE_LSBFIRST); #endif + +#ifdef RENDER + if(info->RenderAccel && ((pScrn->bitsPerPixel == 32) || (pScrn->bitsPerPixel == 16))) { + a->CPUToScreenAlphaTextureFlags = XAA_RENDER_NO_TILE; + a->CPUToScreenAlphaTextureFormats = RADEONAlphaTextureFormats; + a->CPUToScreenTextureFlags = XAA_RENDER_NO_TILE; + a->CPUToScreenTextureFormats = RADEONTextureFormats; + + if (IS_R300_VARIANT) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XRender for R9700/9500 and newer cards is not supported\n"); + return; + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + a->SetupForCPUToScreenAlphaTexture = FUNC_NAME(R200SetupForCPUToScreenAlphaTexture); + a->SubsequentCPUToScreenAlphaTexture = FUNC_NAME(R200SubsequentCPUToScreenTexture); + + a->SetupForCPUToScreenTexture = FUNC_NAME(R200SetupForCPUToScreenTexture); + a->SubsequentCPUToScreenTexture = FUNC_NAME(R200SubsequentCPUToScreenTexture); + } else { + a->SetupForCPUToScreenAlphaTexture = FUNC_NAME(R100SetupForCPUToScreenAlphaTexture); + a->SubsequentCPUToScreenAlphaTexture = FUNC_NAME(R100SubsequentCPUToScreenTexture); + + a->SetupForCPUToScreenTexture = FUNC_NAME(R100SetupForCPUToScreenTexture); + a->SubsequentCPUToScreenTexture = FUNC_NAME(R100SubsequentCPUToScreenTexture); + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XRender Acceleration Enabled\n"); + } +#endif } #undef FUNC_NAME --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_render.c.xrender 2004-05-20 10:06:01.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_render.c 2004-05-23 19:56:26.000000000 -0400 @@ -0,0 +1,659 @@ + +#include "dixstruct.h" + +#include "radeon_reg.h" +#include "xaa.h" +#include "xaalocal.h" + +#ifndef RENDER_GENERIC_HELPER +#define RENDER_GENERIC_HELPER + +static long F_TO_DW(float val) +{ + union { + float f; + long l; + } tmp; + tmp.f = val; + return tmp.l; +} + +static void R100Init3DEngine(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + RADEONWaitForFifo(pScrn, 8); + + /* These are a few registers we need to initialize once at the beginning, + Other context sensitive registers have to be renewed for every setup call + */ + if (!info->HasTCL) { + OUTREG(RADEON_SE_CNTL_STATUS, (1<<8)); + } else { + OUTREG(RADEON_SE_CNTL_STATUS, 0); + } +} + +static void R200Init3DEngine(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + RADEONWaitForFifo(pScrn, 8); + + /* These are a few registers we need to initialize once at the beginning, + Other context sensitive registers have to be renewed for every setup call + */ + OUTREG(R200_VF_MAX_VTX_INDX, 0xffffff); + OUTREG(R200_VF_MIN_VTX_INDX, 0x0); + + if (!info->HasTCL) { + OUTREG(RADEON_SE_CNTL_STATUS, (1<<8)); + } else { + OUTREG(RADEON_SE_CNTL_STATUS, 0); + } + + OUTREG(R200_SE_TCL_OUTPUT_VTX_COMP_ENABLE, 0x0); + OUTREG(R200_PP_CNTL_X, 0); + OUTREG(R200_PP_TXMULTI_CTL_0, 0); + OUTREG(R200_SE_VTX_STATE_CNTL, 0); +} + +void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR (pScrn); + if (IS_R300_VARIANT) { + /*R300Init3DEngine (pScrn);*/ + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + R200Init3DEngine (pScrn); + } else { + R100Init3DEngine (pScrn); + } +} + +static void +RemoveLinear (FBLinearPtr linear) +{ + RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr); + + info->RenderTex = NULL; +} + +static void +RenderCallback (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + + if((currentTime.milliseconds > info->RenderTime) && info->RenderTex) { + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + + if(!info->RenderTex) + info->RenderCallback = NULL; +} + +static Bool +AllocateLinear ( + ScrnInfoPtr pScrn, + int sizeNeeded +){ + RADEONInfoPtr info = RADEONPTR(pScrn); + + info->RenderTime = currentTime.milliseconds + 30000; + info->RenderCallback = RenderCallback; + + if(info->RenderTex) { + if(info->RenderTex->size >= sizeNeeded) + return TRUE; + else { + if(xf86ResizeOffscreenLinear(info->RenderTex, sizeNeeded)) + return TRUE; + + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + } + + info->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32, + NULL, RemoveLinear, info); + + return (info->RenderTex != NULL); +} + +static int texwidth, texheight; +#endif + +#if defined(ACCEL_MMIO) && defined(ACCEL_CP) +#error Cannot define both MMIO and CP acceleration! +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + +#ifdef ACCEL_MMIO +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) +#else +#ifdef ACCEL_CP +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) +#else +#error No accel type defined! +#endif +#endif + +static Bool +FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaType, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int pitch, offset; + CARD32 format, txsize; + ACCEL_PREAMBLE(); + + if(op != PictOpOver) return FALSE; + + /*xf86DrvMsg(0, X_INFO, "alphasetup: %d %d %d %d %d %d\n", red, green, blue, alpha, width, height);*/ + if((width > 2048) || (height > 2048)) + return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = RADEON_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = RADEON_COLOR_FORMAT_RGB565 ; + } + + + XAA_888_plus_PICT_a8_to_8888( + (blue >> 8) | (green & 0xff00) | ((red & 0xff00) << 8), + alphaPtr, alphaPitch, (CARD32*)(info->FB + offset), + pitch, width, height); + + + BEGIN_ACCEL(17); + + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, + RADEON_SRC_BLEND_GL_SRC_ALPHA | + RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA); + + OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(RADEON_RB3D_ZSTENCILCNTL, 0); + + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); + + OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, (RADEON_TXFORMAT_ARGB8888 | + RADEON_TXFORMAT_NON_POWER2 | + RADEON_TXFORMAT_ALPHA_IN_MAP)); + OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, (RADEON_MAG_FILTER_LINEAR | + RADEON_MIN_FILTER_LINEAR | + RADEON_CLAMP_S_CLAMP_LAST | + RADEON_CLAMP_T_CLAMP_LAST)); + OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR); + OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA); + + OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, (1<<8)); + OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0); + + FINISH_ACCEL(); + + return TRUE; +} + + +static Bool +FUNC_NAME(R100SetupForCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int op, + int texType, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int pitch, offset, i; + CARD32 format, txsize; + CARD8 *dst; + ACCEL_PREAMBLE(); + + if(op != PictOpOver) return FALSE; + + if((width > 2048) || (height > 2048)) return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = RADEON_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = RADEON_COLOR_FORMAT_RGB565 ; + } + + i = height; + dst = (CARD8*)(info->FB + offset); + while(i--) { + memcpy(dst, texPtr, width << 2); + texPtr += texPitch; + dst += pitch << 2; + } + + BEGIN_ACCEL(37); + + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format); + OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(RADEON_RB3D_ZSTENCILCNTL, 0); + + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); + + OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, (RADEON_TXFORMAT_ARGB8888 | + RADEON_TXFORMAT_NON_POWER2 | + RADEON_TXFORMAT_ALPHA_IN_MAP)); + OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(RADEON_PP_TEX_PITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, (RADEON_MAG_FILTER_LINEAR | + RADEON_MIN_FILTER_LINEAR | + RADEON_CLAMP_S_CLAMP_LAST | + RADEON_CLAMP_T_CLAMP_LAST)); + OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, RADEON_COLOR_ARG_C_T0_COLOR); + OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, RADEON_ALPHA_ARG_C_T0_ALPHA); + + OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, (1<<8)); + OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0); + + FINISH_ACCEL(); + + return FALSE; +} + + +static void +FUNC_NAME(R100SubsequentCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int bytepp; + float l, t, r, b, fl, fr, ft, fb; + float one = 0.0; + + ACCEL_PREAMBLE(); + + bytepp = (pScrn->bitsPerPixel>>4); + l=((dstx<>bytepp; t=0.0; r=(float)width+l; b=(float)height; + fl=(float)srcx/(float)texwidth; + fr=(float)(srcx+width)/(float)texwidth; + ft=(float)srcy/(float)texheight; + fb=(float)(srcy+height)/(float)texheight; + + BEGIN_ACCEL(20); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + */ + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth*dsty+dstx)<accel->NeedToSync = TRUE; +} + + +static Bool +FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaType, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int pitch, offset; + CARD32 format, txsize; + ACCEL_PREAMBLE(); + + if(op != PictOpOver) return FALSE; + + if((width > 2048) || (height > 2048)) + return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = RADEON_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = RADEON_COLOR_FORMAT_RGB565 ; + } + + XAA_888_plus_PICT_a8_to_8888( + (blue >> 8) | (green & 0xff00) | ((red & 0xff00) << 8), + alphaPtr, alphaPitch, (CARD32*)(info->FB + offset), + pitch, width, height); + + BEGIN_ACCEL(18); + + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format | RADEON_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, + RADEON_SRC_BLEND_GL_SRC_ALPHA | + RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA); + OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(RADEON_SE_COORD_FMT, 0x0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); + OUT_ACCEL_REG(RADEON_RB3D_ZSTENCILCNTL, 0); + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_VF_MAX_VTX_NUM); + + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE); + + OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, (RADEON_TXFORMAT_ARGB8888 | + RADEON_TXFORMAT_NON_POWER2 | + RADEON_TXFORMAT_ALPHA_IN_MAP)); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); + OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, (RADEON_MAG_FILTER_LINEAR | + RADEON_MIN_FILTER_LINEAR | + RADEON_CLAMP_S_CLAMP_LAST | + RADEON_CLAMP_T_CLAMP_LAST)); + + OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2< 2048) || (height > 2048)) return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = RADEON_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = RADEON_COLOR_FORMAT_RGB565 ; + } + + i = height; + dst = (CARD8*)(info->FB + offset); + while(i--) { + memcpy(dst, texPtr, width << 2); + texPtr += texPitch; + dst += pitch << 2; + } + + BEGIN_ACCEL(17); + + OUT_ACCEL_REG(RADEON_RB3D_CNTL, format); + OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | + RADEON_BFACE_SOLID | + RADEON_FFACE_SOLID | + RADEON_VTX_PIX_CENTER_OGL | + RADEON_ROUND_MODE_ROUND | + RADEON_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(RADEON_SE_COORD_FMT, 0x0); + OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); + OUT_ACCEL_REG(RADEON_RB3D_ZSTENCILCNTL, 0); + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_VF_MAX_VTX_NUM); + + OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE); + + OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, (RADEON_TXFORMAT_ARGB8888 | + RADEON_TXFORMAT_NON_POWER2 | + RADEON_TXFORMAT_ALPHA_IN_MAP)); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); + OUT_ACCEL_REG(RADEON_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, (RADEON_MAG_FILTER_LINEAR | + RADEON_MIN_FILTER_LINEAR | + RADEON_CLAMP_S_CLAMP_LAST | + RADEON_CLAMP_T_CLAMP_LAST)); + + OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2<bitsPerPixel>>4); + l=((dstx<>bytepp; t=0.0; r=(float)width+l; b=(float)height; + fl=(float)srcx/(float)texwidth; + fr=(float)(srcx+width)/(float)texwidth; + ft=(float)srcy/(float)texheight; + fb=(float)(srcy+height)/(float)texheight; + + BEGIN_ACCEL(20); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + */ + OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth*dsty+dstx)<accel->NeedToSync = TRUE; + +} + +#undef FUNC_NAME + --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man.xrender 2004-05-10 09:42:44.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man 2004-05-24 23:12:58.000000000 -0400 @@ -329,6 +329,43 @@ .B frequency parameter may be specified as a float value with standard suffixes like "k", "kHz", "M", "MHz". +.TP +.BI "Option \*qRenderAccel\*q \*q" boolean \*q +Enable XRender acceleration, currently it does not work on 9700/9500 +and newer cards. Note when using a digital panel, subpixel RGB +decimation is enabled by default, the render acceleration is +effectively turned off by XAA. Option SubPixelOrder can be used to +disable subpixel decimation. Since render acceleration on radeon +cards is still in test stage, the default is +.B off. +.TP +.BI "Option \*qSubPixelOrder\*q \*q" "string" \*q +Force subpixel order to specified order. +Subpixel order is used for subpixel decimation on flat panels. +.br +NONE \-\- No subpixel (CRT like displays) +.br +RGB \-\- in horizontal RGB order (most flat panels) +.br +BGR \-\- in horizontal BGR order (some flat panels) + +.br +This option is intended to be used in following cases: +.br +1. The default subpixel order is incorrect for your panel. +.br +2. Enable subpixel decimation on analog panels. +.br +3. Adjust to one display type in dual-head clone mode setup. +.br +4. Get better performance with XRender acceleration on +digital panels (use NONE setting). +.br +The default is +.B NONE +for CRT, +.B RGB +for digital panels .SH SEE ALSO XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h.xrender 2004-05-20 11:23:44.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 2004-05-23 19:55:24.000000000 -0400 @@ -1953,7 +1953,109 @@ #define RADEON_SE_ZBIAS_FACTOR 0x1db0 #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 - +#define RADEON_SE_VTX_FMT 0x2080 +# define RADEON_SE_VTX_FMT_XY 0x00000000 +# define RADEON_SE_VTX_FMT_W0 0x00000001 +# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 +# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 +# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 +# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 +# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 +# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 +# define RADEON_SE_VTX_FMT_ST0 0x00000080 +# define RADEON_SE_VTX_FMT_ST1 0x00000100 +# define RADEON_SE_VTX_FMT_Q1 0x00000200 +# define RADEON_SE_VTX_FMT_ST2 0x00000400 +# define RADEON_SE_VTX_FMT_Q2 0x00000800 +# define RADEON_SE_VTX_FMT_ST3 0x00001000 +# define RADEON_SE_VTX_FMT_Q3 0x00002000 +# define RADEON_SE_VTX_FMT_Q0 0x00004000 +# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +# define RADEON_SE_VTX_FMT_N0 0x00040000 +# define RADEON_SE_VTX_FMT_XY1 0x08000000 +# define RADEON_SE_VTX_FMT_Z1 0x10000000 +# define RADEON_SE_VTX_FMT_W1 0x20000000 +# define RADEON_SE_VTX_FMT_N1 0x40000000 +# define RADEON_SE_VTX_FMT_Z 0x80000000 + +#define RADEON_SE_VF_CNTL 0x2084 +# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 +# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 +# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 +# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 +# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 +# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 +# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 +# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 +# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 +# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 +# define RADEON_VF_PRIM_TYPE_POLYGON 15 +# define RADEON_VF_PRIM_WALK_STATE (0<<4) +# define RADEON_VF_PRIM_WALK_INDEX (1<<4) +# define RADEON_VF_PRIM_WALK_LIST (2<<4) +# define RADEON_VF_PRIM_WALK_DATA (3<<4) +# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) +# define RADEON_VF_RADEON_MODE (1<<7) +# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) +# define RADEON_VF_PROG_STREAM_ENA (1<<10) +# define RADEON_VF_INDEX_SIZE_SHIFT 11 +# define RADEON_VF_NUM_VERTICES_SHIFT 16 + +#define RADEON_SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +# define R200_VAP_TCL_ENABLE (1<<0) +# define R200_VAP_HOS_ENABLE (1<<1) +# define R200_VAP_PVS_ENABLE (1<<2) +# define R200_VAP_FORCE_W_TO_ONE (1<<16) +# define R200_VAP_VF_MAX_VTX_NUM (9<<18) +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +# define R200_SE_VTE_VPORT_X_SCALE_ENA 0x00000001 +# define R200_SE_VTE_VPORT_X_OFFSET_ENA 0x00000002 +# define R200_SE_VTE_VPORT_Y_SCALE_ENA 0x00000004 +# define R200_SE_VTE_VPORT_Y_OFFSET_ENA 0x00000008 +# define R200_SE_VTE_VPORT_Z_SCALE_ENA 0x00000010 +# define R200_SE_VTE_VPORT_Z_OFFSET_ENA 0x00000020 +# define R200_SE_VTE_VTX_XY_FMT 0x00000100 +# define R200_SE_VTE_VTX_Z_FMT 0x00000200 +# define R200_SE_VTE_VTX_W0_FMT 0x00000400 +# define R200_SE_VTE_VTX_W0_NORMALIZE 0x00000800 +# define R200_SE_VTE_VTX_ST_DENORMALIZED 0x00001000 +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXPITCH_0 0x2c10 +#define R200_SE_VTX_FMT_0 0x2088 +#define R200_SE_VTX_FMT_1 0x208c +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +# define R200_VTX_Z0_PRESENT (1<<0) +# define R200_VTX_W0_PRESENT (1<<1) +# define R200_VTX_N0_PRESENT (1<<6) +# define R200_VTX_COLOR0_FMT_PACKED (1<<11) +# define R200_VTX_COLOR0_FMT_F3 (2<<11) +# define R200_VTX_COLOR0_FMT_F4 (3<<11) +# define R200_VTX_COLOR1_FMT_PACKED (1<<13) +# define R200_VTX_COLOR1_FMT_F3 (2<<13) +# define R200_VTX_COLOR1_FMT_F4 (3<<13) +# define R200_VTX_TEX_0_COMP_CNT__SHIFT 0 +# define R200_VTX_TEX_1_COMP_CNT__SHIFT 3 +# define R200_VTX_TEX_2_COMP_CNT__SHIFT 6 +# define R200_VTX_TEX_3_COMP_CNT__SHIFT 9 +# define R200_VTX_TEX_4_COMP_CNT__SHIFT 12 +# define R200_VTX_TEX_5_COMP_CNT__SHIFT 15 +#define R200_SE_TCL_OUTPUT_VTX_COMP_ENABLE 0x2250 +# define R200_SE_TCL_COMP_ENABLE_XYZW 1 +# define R200_SE_TCL_COMP_ENABLE_COLOR0 (1<<8) +# define R200_SE_TCL_COMP_ENABLE_COLOR1 (1<<9) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) /* Registers for CP and Microcode Engine */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c.xrender 2004-05-20 10:22:13.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c 2004-05-20 13:28:54.000000000 -0400 @@ -110,6 +110,9 @@ { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ }; +static CARD32 RADEONAlphaTextureFormats[2] = {PICT_a8, 0}; +static CARD32 RADEONTextureFormats[2] = {PICT_a8r8g8b8, 0}; + extern int gRADEONEntityIndex; /* The FIFO has 64 slots. This routines waits until at least `entries' @@ -377,6 +380,10 @@ #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define FINISH_ACCEL() +#ifdef RENDER +#include "radeon_render.c" +#endif + #include "radeon_accelfuncs.c" #undef ACCEL_MMIO @@ -395,6 +402,9 @@ #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() +#ifdef RENDER +#include "radeon_render.c" +#endif #include "radeon_accelfuncs.c" #undef ACCEL_CP --- xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_driver.c.xrender 2004-05-20 10:03:39.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_driver.c 2004-05-21 10:51:32.000000000 -0400 @@ -133,6 +133,9 @@ { OPTION_REVERSE_DISPLAY,"ReverseDisplay", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_NOBIOS, "NoBIOS", OPTV_BOOLEAN, {0}, FALSE }, { OPTION_REF_CLOCK, "RefClock", OPTV_INTEGER, {0}, FALSE }, +#ifdef RENDER + { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, +#endif { -1, NULL, OPTV_NONE, {0}, FALSE } }; @@ -1003,7 +1006,17 @@ info->IsIGP = FALSE; info->BusType = -1; info->HasSingleDAC = FALSE; + info->HasTCL = FALSE; switch (info->Chipset) { + case PCI_CHIP_RADEON_QD: + case PCI_CHIP_RADEON_QE: + case PCI_CHIP_RADEON_QF: + case PCI_CHIP_RADEON_QG: + info->ChipFamily = CHIP_FAMILY_RADEON; + info->HasTCL = TRUE; + info->HasCRTC2 = FALSE; + break; + case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: info->IsMobility = TRUE; @@ -1042,6 +1055,7 @@ case PCI_CHIP_R200_QL: case PCI_CHIP_R200_QM: info->ChipFamily = CHIP_FAMILY_R200; + info->HasTCL = TRUE; break; case PCI_CHIP_RADEON_LW: @@ -1050,6 +1064,7 @@ case PCI_CHIP_RV200_QW: /* RV200 desktop */ case PCI_CHIP_RV200_QX: info->ChipFamily = CHIP_FAMILY_RV200; + info->HasTCL = TRUE; break; case PCI_CHIP_RV250_Ld: @@ -1059,6 +1074,7 @@ case PCI_CHIP_RV250_If: case PCI_CHIP_RV250_Ig: info->ChipFamily = CHIP_FAMILY_RV250; + info->HasTCL = TRUE; break; case PCI_CHIP_RS300_5835: @@ -1079,6 +1095,7 @@ case PCI_CHIP_RV280_5962: case PCI_CHIP_RV280_5964: info->ChipFamily = CHIP_FAMILY_RV280; + info->HasTCL = TRUE; break; case PCI_CHIP_R300_AD: @@ -1090,6 +1107,7 @@ case PCI_CHIP_R300_NF: case PCI_CHIP_R300_NG: info->ChipFamily = CHIP_FAMILY_R300; + info->HasTCL = TRUE; break; case PCI_CHIP_RV350_NP: @@ -1106,6 +1124,7 @@ case PCI_CHIP_RV350_AT: case PCI_CHIP_RV350_AV: info->ChipFamily = CHIP_FAMILY_RV350; + info->HasTCL = TRUE; break; case PCI_CHIP_R350_AH: @@ -1117,6 +1136,7 @@ case PCI_CHIP_R350_NK: case PCI_CHIP_R360_NJ: info->ChipFamily = CHIP_FAMILY_R350; + info->HasTCL = TRUE; break; case PCI_CHIP_RV380_3150: @@ -1126,6 +1146,7 @@ case PCI_CHIP_RV380_3E54: info->ChipFamily = CHIP_FAMILY_RV380; info->BusType = BUS_TYPE_PCIE; + info->HasTCL = TRUE; break; case PCI_CHIP_RV370_5460: @@ -1136,6 +1157,7 @@ case PCI_CHIP_RV370_5B65: info->ChipFamily = CHIP_FAMILY_RV380; info->BusType = BUS_TYPE_PCIE; + info->HasTCL = TRUE; break; case PCI_CHIP_R420_JN: @@ -1148,6 +1170,7 @@ case PCI_CHIP_R420_JM: case PCI_CHIP_R420_JP: info->ChipFamily = CHIP_FAMILY_R420; + info->HasTCL = TRUE; break; case PCI_CHIP_R423_UH: @@ -1160,12 +1183,11 @@ case PCI_CHIP_R423_5D57: info->ChipFamily = CHIP_FAMILY_R420; info->BusType = BUS_TYPE_PCIE; + info->HasTCL = TRUE; break; default: - /* Original Radeon/7200 */ - info->ChipFamily = CHIP_FAMILY_RADEON; - info->HasCRTC2 = FALSE; + return FALSE; } /* Framebuffer */ @@ -2431,6 +2453,10 @@ } #endif +#ifdef RENDER + info->RenderAccel = xf86ReturnOptValBool (info->Options, OPTION_RENDER_ACCEL, FALSE); +#endif + return TRUE; } @@ -3002,6 +3028,12 @@ if (info->VideoTimerCallback) (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); + +#ifdef RENDER + if(info->RenderCallback) + (*info->RenderCallback)(pScrn); +#endif + } /* Called at the start of each server generation. */ @@ -3464,6 +3496,9 @@ xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); } +#ifdef RENDER + if (info->RenderAccel) RADEONInit3DEngineForRender(pScrn); +#endif /* Colormap setup */ if (!miCreateDefColormap(pScreen)) return FALSE; if (!xf86HandleColormaps(pScreen, 256, info->dac6bits ? 6 : 8, @@ -3722,7 +3757,6 @@ unsigned char *RADEONMMIO = info->MMIO; unsigned long tmp; - OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl); OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl); OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch); @@ -4366,7 +4400,7 @@ save->disp2_base_addr = 0; save->ov0_base_addr = 0; } - + info->fbLocation = (save->mc_fb_location & 0xffff) << 16; } static void RADEONInitFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, BOOL IsPrimary) @@ -5498,6 +5532,11 @@ } #endif + if(info->RenderTex) { + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + if (pScrn->vtSema) { RADEONRestore(pScrn); } --- xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_accelfuncs.c.xrender 2004-05-20 10:04:05.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_accelfuncs.c 2004-05-20 12:01:37.000000000 -0400 @@ -1346,6 +1346,36 @@ | HARDWARE_PATTERN_SCREEN_ORIGIN | BIT_ORDER_IN_BYTE_LSBFIRST); #endif + +#ifdef RENDER + if(info->RenderAccel && ((pScrn->bitsPerPixel == 32) || (pScrn->bitsPerPixel == 16))) { + a->CPUToScreenAlphaTextureFlags = XAA_RENDER_NO_TILE; + a->CPUToScreenAlphaTextureFormats = RADEONAlphaTextureFormats; + a->CPUToScreenTextureFlags = XAA_RENDER_NO_TILE; + a->CPUToScreenTextureFormats = RADEONTextureFormats; + + if (IS_R300_VARIANT) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XRender for R9700/9500 and newer cards is not supported\n"); + return; + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + a->SetupForCPUToScreenAlphaTexture = FUNC_NAME(R200SetupForCPUToScreenAlphaTexture); + a->SubsequentCPUToScreenAlphaTexture = FUNC_NAME(R200SubsequentCPUToScreenTexture); + + a->SetupForCPUToScreenTexture = FUNC_NAME(R200SetupForCPUToScreenTexture); + a->SubsequentCPUToScreenTexture = FUNC_NAME(R200SubsequentCPUToScreenTexture); + } else { + a->SetupForCPUToScreenAlphaTexture = FUNC_NAME(R100SetupForCPUToScreenAlphaTexture); + a->SubsequentCPUToScreenAlphaTexture = FUNC_NAME(R100SubsequentCPUToScreenTexture); + + a->SetupForCPUToScreenTexture = FUNC_NAME(R100SetupForCPUToScreenTexture); + a->SubsequentCPUToScreenTexture = FUNC_NAME(R100SubsequentCPUToScreenTexture); + } + xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XRender Acceleration Enabled\n"); + } +#endif } #undef FUNC_NAME --- xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_render.c.xrender 2004-05-20 10:06:01.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_render.c 2004-05-21 06:14:21.000000000 -0400 @@ -0,0 +1,660 @@ + +#include "dixstruct.h" + +#include "r100reg.h" +#include "r200reg.h" +#include "radeon_reg.h" +#include "xaa.h" +#include "xaalocal.h" + +#ifndef RENDER_GENERIC_HELPER +#define RENDER_GENERIC_HELPER + +static long F_TO_DW(float val) +{ + union { + float f; + long l; + } tmp; + tmp.f = val; + return tmp.l; +} + +static void R100Init3DEngine(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + RADEONWaitForFifo(pScrn, 8); + + /* These are a few registers we need to initialize once at the beginning, + Other context sensitive registers have to be renewed for every setup call + */ + if (!info->HasTCL) { + OUTREG(R100_SE_CNTL_STATUS, (1<<8)); + } else { + OUTREG(R100_SE_CNTL_STATUS, 0); + } +} + +static void R200Init3DEngine(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + RADEONWaitForFifo(pScrn, 8); + + /* These are a few registers we need to initialize once at the beginning, + Other context sensitive registers have to be renewed for every setup call + */ + OUTREG(R200_VF_MAX_VTX_INDX, 0xffffff); + OUTREG(R200_VF_MIN_VTX_INDX, 0x0); + + if (!info->HasTCL) { + OUTREG(R200_SE_VAP_CNTL_STATUS, (1<<8)); + } else { + OUTREG(R200_SE_VAP_CNTL_STATUS, 0); + } + + OUTREG(R200_SE_TCL_OUTPUT_VTX_COMP_ENABLE, 0x0); + OUTREG(R200_PP_CNTL_X, 0); + OUTREG(R200_PP_TXMULTI_CTL_0, 0); + OUTREG(R200_SE_VTX_STATE_CNTL, 0); +} + +void RADEONInit3DEngineForRender(ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR (pScrn); + if (IS_R300_VARIANT) { + /*R300Init3DEngine (pScrn);*/ + } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || + (info->ChipFamily == CHIP_FAMILY_RV280) || + (info->ChipFamily == CHIP_FAMILY_RS300) || + (info->ChipFamily == CHIP_FAMILY_R200)) { + R200Init3DEngine (pScrn); + } else { + R100Init3DEngine (pScrn); + } +} + +static void +RemoveLinear (FBLinearPtr linear) +{ + RADEONInfoPtr info = (RADEONInfoPtr)(linear->devPrivate.ptr); + + info->RenderTex = NULL; +} + +static void +RenderCallback (ScrnInfoPtr pScrn) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + + if((currentTime.milliseconds > info->RenderTime) && info->RenderTex) { + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + + if(!info->RenderTex) + info->RenderCallback = NULL; +} + +static Bool +AllocateLinear ( + ScrnInfoPtr pScrn, + int sizeNeeded +){ + RADEONInfoPtr info = RADEONPTR(pScrn); + + info->RenderTime = currentTime.milliseconds + 30000; + info->RenderCallback = RenderCallback; + + if(info->RenderTex) { + if(info->RenderTex->size >= sizeNeeded) + return TRUE; + else { + if(xf86ResizeOffscreenLinear(info->RenderTex, sizeNeeded)) + return TRUE; + + xf86FreeOffscreenLinear(info->RenderTex); + info->RenderTex = NULL; + } + } + + info->RenderTex = xf86AllocateOffscreenLinear(pScrn->pScreen, sizeNeeded, 32, + NULL, RemoveLinear, info); + + return (info->RenderTex != NULL); +} + +static int texwidth, texheight; +#endif + +#if defined(ACCEL_MMIO) && defined(ACCEL_CP) +#error Cannot define both MMIO and CP acceleration! +#endif + +#if !defined(UNIXCPP) || defined(ANSICPP) +#define FUNC_NAME_CAT(prefix,suffix) prefix##suffix +#else +#define FUNC_NAME_CAT(prefix,suffix) prefix/**/suffix +#endif + +#ifdef ACCEL_MMIO +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,MMIO) +#else +#ifdef ACCEL_CP +#define FUNC_NAME(prefix) FUNC_NAME_CAT(prefix,CP) +#else +#error No accel type defined! +#endif +#endif + +static Bool +FUNC_NAME(R100SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaType, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int pitch, offset; + CARD32 format, txsize; + ACCEL_PREAMBLE(); + + if(op != PictOpOver) return FALSE; + + /*xf86DrvMsg(0, X_INFO, "alphasetup: %d %d %d %d %d %d\n", red, green, blue, alpha, width, height);*/ + if((width > 2048) || (height > 2048)) + return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = R100_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = R100_COLOR_FORMAT_RGB565 ; + } + + + XAA_888_plus_PICT_a8_to_8888( + (blue >> 8) | (green & 0xff00) | ((red & 0xff00) << 8), + alphaPtr, alphaPitch, (CARD32*)(info->FB + offset), + pitch, width, height); + + + BEGIN_ACCEL(17); + + OUT_ACCEL_REG(R100_RB3D_CNTL, format | R100_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(R100_RB3D_BLENDCNTL, + R100_SRC_BLEND_GL_SRC_ALPHA | + R100_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA); + + OUT_ACCEL_REG(R100_SE_CNTL, (R100_DIFFUSE_SHADE_GOURAUD | + R100_BFACE_SOLID | + R100_FFACE_SOLID | + R100_VTX_PIX_CENTER_OGL | + R100_ROUND_MODE_ROUND | + R100_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(R100_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(R100_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(R100_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(R100_RB3D_ZSTENCILCNTL, 0); + + OUT_ACCEL_REG(R100_PP_CNTL, R100_TEX_0_ENABLE | R100_TEX_BLEND_0_ENABLE); + + OUT_ACCEL_REG(R100_PP_TXFORMAT_0, (R100_TXF_32BPP_ARGB8888 | + R100_TXF_NON_POWER2 | + R100_TXF_ALPHA_IN_MAP)); + OUT_ACCEL_REG(R100_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(R100_PP_TEX_PITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(R100_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(R100_PP_TXFILTER_0, (R100_MAG_FILTER_LINEAR | + R100_MIN_FILTER_LINEAR | + R100_CLAMP_S_CLAMP_LAST | + R100_CLAMP_T_CLAMP_LAST)); + OUT_ACCEL_REG(R100_PP_TXCBLEND_0, R100_COLOR_ARG_C_T0_COLOR); + OUT_ACCEL_REG(R100_PP_TXABLEND_0, R100_ALPHA_ARG_C_T0_ALPHA); + + OUT_ACCEL_REG(R100_SE_CNTL_STATUS, (1<<8)); + OUT_ACCEL_REG(R100_SE_VTX_FMT, R100_SE_VTX_FMT_XY | R100_SE_VTX_FMT_ST0); + + FINISH_ACCEL(); + + return TRUE; +} + + +static Bool +FUNC_NAME(R100SetupForCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int op, + int texType, + CARD8 *texPtr, + int texPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int pitch, offset, i; + CARD32 format, txsize; + CARD8 *dst; + ACCEL_PREAMBLE(); + + if(op != PictOpOver) return FALSE; + + if((width > 2048) || (height > 2048)) return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = R100_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = R100_COLOR_FORMAT_RGB565 ; + } + + i = height; + dst = (CARD8*)(info->FB + offset); + while(i--) { + memcpy(dst, texPtr, width << 2); + texPtr += texPitch; + dst += pitch << 2; + } + + BEGIN_ACCEL(37); + + OUT_ACCEL_REG(R100_RB3D_CNTL, format); + OUT_ACCEL_REG(R100_SE_CNTL, (R100_DIFFUSE_SHADE_GOURAUD | + R100_BFACE_SOLID | + R100_FFACE_SOLID | + R100_VTX_PIX_CENTER_OGL | + R100_ROUND_MODE_ROUND | + R100_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(R100_RE_TOP_LEFT, 0); + OUT_ACCEL_REG(R100_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(R100_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(R100_RB3D_ZSTENCILCNTL, 0); + + OUT_ACCEL_REG(R100_PP_CNTL, R100_TEX_0_ENABLE | R100_TEX_BLEND_0_ENABLE); + + OUT_ACCEL_REG(R100_PP_TXFORMAT_0, (R100_TXF_32BPP_ARGB8888 | + R100_TXF_NON_POWER2 | + R100_TXF_ALPHA_IN_MAP)); + OUT_ACCEL_REG(R100_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(R100_PP_TEX_PITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(R100_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(R100_PP_TXFILTER_0, (R100_MAG_FILTER_LINEAR | + R100_MIN_FILTER_LINEAR | + R100_CLAMP_S_CLAMP_LAST | + R100_CLAMP_T_CLAMP_LAST)); + OUT_ACCEL_REG(R100_PP_TXCBLEND_0, R100_COLOR_ARG_C_T0_COLOR); + OUT_ACCEL_REG(R100_PP_TXABLEND_0, R100_ALPHA_ARG_C_T0_ALPHA); + + OUT_ACCEL_REG(R100_SE_CNTL_STATUS, (1<<8)); + OUT_ACCEL_REG(R100_SE_VTX_FMT, R100_SE_VTX_FMT_XY | R100_SE_VTX_FMT_ST0); + + FINISH_ACCEL(); + + return FALSE; +} + + +static void +FUNC_NAME(R100SubsequentCPUToScreenTexture) ( + ScrnInfoPtr pScrn, + int dstx, + int dsty, + int srcx, + int srcy, + int width, + int height +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int bytepp; + float l, t, r, b, fl, fr, ft, fb; + float one = 0.0; + + ACCEL_PREAMBLE(); + + bytepp = (pScrn->bitsPerPixel>>4); + l=((dstx<>bytepp; t=0.0; r=(float)width+l; b=(float)height; + fl=(float)srcx/(float)texwidth; + fr=(float)(srcx+width)/(float)texwidth; + ft=(float)srcy/(float)texheight; + fb=(float)(srcy+height)/(float)texheight; + + BEGIN_ACCEL(20); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + */ + OUT_ACCEL_REG(R100_RB3D_COLOROFFSET, (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth*dsty+dstx)<accel->NeedToSync = TRUE; +} + + +static Bool +FUNC_NAME(R200SetupForCPUToScreenAlphaTexture) ( + ScrnInfoPtr pScrn, + int op, + CARD16 red, + CARD16 green, + CARD16 blue, + CARD16 alpha, + int alphaType, + CARD8 *alphaPtr, + int alphaPitch, + int width, + int height, + int flags +) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + int pitch, offset; + CARD32 format, txsize; + ACCEL_PREAMBLE(); + + if(op != PictOpOver) return FALSE; + + if((width > 2048) || (height > 2048)) + return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = R200_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = R200_COLOR_FORMAT_RGB565 ; + } + + XAA_888_plus_PICT_a8_to_8888( + (blue >> 8) | (green & 0xff00) | ((red & 0xff00) << 8), + alphaPtr, alphaPitch, (CARD32*)(info->FB + offset), + pitch, width, height); + + BEGIN_ACCEL(18); + + OUT_ACCEL_REG(R200_RB3D_CNTL, format | R200_ALPHA_BLEND_ENABLE); + OUT_ACCEL_REG(R200_RB3D_BLENDCNTL, + R200_SRC_BLEND_GL_SRC_ALPHA | + R200_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA); + OUT_ACCEL_REG(R200_SE_CNTL, (R200_DIFFUSE_SHADE_GOURAUD | + R200_BFACE_SOLID | + R200_FFACE_SOLID | + R200_VTX_PIX_CENTER_OGL | + R200_ROUND_MODE_ROUND | + R200_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(R200_RE_CNTL, 0x0); + OUT_ACCEL_REG(R200_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(R200_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); + OUT_ACCEL_REG(R200_RB3D_ZSTENCILCNTL, 0); + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_VF_MAX_VTX_NUM); + + OUT_ACCEL_REG(R200_PP_CNTL, R200_TEX_0_ENABLE); + + OUT_ACCEL_REG(R200_PP_TXFORMAT_0, (R200_TXF_32BPP_ARGB8888 | + R200_TXF_NON_POWER2 | + R200_TXF_ALPHA_IN_MAP)); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); + OUT_ACCEL_REG(R200_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(R200_PP_TXFILTER_0, (R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR | + R200_CLAMP_S_CLAMP_LAST | + R200_CLAMP_T_CLAMP_LAST)); + + OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2< 2048) || (height > 2048)) return FALSE; + + pitch = (width + 7) & ~7; + txsize = pitch*height; + if (pScrn->bitsPerPixel == 16) txsize <<= 1; + + if(info->accel->NeedToSync) info->accel->Sync(pScrn); + + if(!AllocateLinear(pScrn, txsize)) return FALSE; + + texwidth = width; + texheight = height; + if (pScrn->bitsPerPixel == 32) { + offset = info->RenderTex->offset<<2; + format = R200_COLOR_FORMAT_ARGB8888; + } else { + offset = info->RenderTex->offset<<1; + format = R200_COLOR_FORMAT_RGB565 ; + } + + i = height; + dst = (CARD8*)(info->FB + offset); + while(i--) { + memcpy(dst, texPtr, width << 2); + texPtr += texPitch; + dst += pitch << 2; + } + + BEGIN_ACCEL(17); + + OUT_ACCEL_REG(R200_RB3D_CNTL, format); + OUT_ACCEL_REG(R200_SE_CNTL, (R200_DIFFUSE_SHADE_GOURAUD | + R200_BFACE_SOLID | + R200_FFACE_SOLID | + R200_VTX_PIX_CENTER_OGL | + R200_ROUND_MODE_ROUND | + R200_ROUND_PREC_4TH_PIX)); + + OUT_ACCEL_REG(R200_RE_CNTL, 0x0); + OUT_ACCEL_REG(R200_RE_WIDTH_HEIGHT, 0x07ff07ff); + + OUT_ACCEL_REG(R200_RB3D_COLORPITCH, pScrn->displayWidth); + OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); + OUT_ACCEL_REG(R200_RB3D_ZSTENCILCNTL, 0); + OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_VF_MAX_VTX_NUM); + + OUT_ACCEL_REG(R200_PP_CNTL, R200_TEX_0_ENABLE); + + OUT_ACCEL_REG(R200_PP_TXFORMAT_0, (R200_TXF_32BPP_ARGB8888 | + R200_TXF_NON_POWER2)); + OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0); + OUT_ACCEL_REG(R200_PP_TEX_SIZE_0, ((height-1)<<16) | (width-1)); + OUT_ACCEL_REG(R200_PP_TXPITCH_0, (pitch<<2)-1); + OUT_ACCEL_REG(R200_PP_TXOFFSET_0, offset + info->fbLocation + pScrn->fbOffset); + OUT_ACCEL_REG(R200_PP_TXFILTER_0, (R200_MAG_FILTER_LINEAR | + R200_MIN_FILTER_LINEAR | + R200_CLAMP_S_CLAMP_LAST | + R200_CLAMP_T_CLAMP_LAST)); + + OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0); + OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2<bitsPerPixel>>4); + l=((dstx<>bytepp; t=0.0; r=(float)width+l; b=(float)height; + fl=(float)srcx/(float)texwidth; + fr=(float)(srcx+width)/(float)texwidth; + ft=(float)srcy/(float)texheight; + fb=(float)(srcy+height)/(float)texheight; + + BEGIN_ACCEL(20); + + /* Note: we can't simply setup 3D surface at the same location as the front buffer, + some apps may draw offscreen pictures out of the limitation of radeon 3D surface. + */ + OUT_ACCEL_REG(R200_RB3D_COLOROFFSET, (info->fbLocation + pScrn->fbOffset + ((pScrn->displayWidth*dsty+dstx)<accel->NeedToSync = TRUE; + +} + +#undef FUNC_NAME + --- xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon.man.xrender 2004-05-21 06:31:12.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon.man 2004-05-10 09:42:44.000000000 -0400 @@ -329,13 +329,6 @@ .B frequency parameter may be specified as a float value with standard suffixes like "k", "kHz", "M", "MHz". -.TP -.BI "Option \*qRenderAccel\*q \*q" boolean \*q -Enable XRender acceleration, currently it does not work on 9700/9500 -and newer cards. Note when using a digital panel, subpixel RGB -decimation is enabled, the acceleration is effectively turned off by XAA. -Since this is still in test stage, the default is -.B off. .SH SEE ALSO XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) --- xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_accel.c.xrender 2004-05-20 10:22:13.000000000 -0400 +++ xc/programs/Xserver/hw/xfree86/drivers/ati.old/radeon_accel.c 2004-05-20 13:28:54.000000000 -0400 @@ -110,6 +110,9 @@ { RADEON_ROP3_ONE, RADEON_ROP3_ONE } /* GXset */ }; +static CARD32 RADEONAlphaTextureFormats[2] = {PICT_a8, 0}; +static CARD32 RADEONTextureFormats[2] = {PICT_a8r8g8b8, 0}; + extern int gRADEONEntityIndex; /* The FIFO has 64 slots. This routines waits until at least `entries' @@ -377,6 +380,10 @@ #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) #define FINISH_ACCEL() +#ifdef RENDER +#include "radeon_render.c" +#endif + #include "radeon_accelfuncs.c" #undef ACCEL_MMIO @@ -395,6 +402,9 @@ #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) #define FINISH_ACCEL() ADVANCE_RING() +#ifdef RENDER +#include "radeon_render.c" +#endif #include "radeon_accelfuncs.c" #undef ACCEL_CP