--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h.misc_orig	2003-10-02 13:26:10.000000000 -0400
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h	2003-10-02 13:29:16.000000000 -0400
@@ -130,6 +130,7 @@
     CARD32            crtc_pitch;
     CARD32            disp_merge_cntl;
     CARD32            grph_buffer_cntl;
+    CARD32            crtc_more_cntl;
 
 				/* CRTC2 registers */
     CARD32            crtc2_gen_cntl;
--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c.misc_orig	2003-10-02 13:15:33.000000000 -0400
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c	2003-10-03 07:59:29.000000000 -0400
@@ -1347,6 +1347,7 @@
 		pRADEONEnt->MonType1 = pRADEONEnt->MonType2;
 		pRADEONEnt->MonInfo1 = pRADEONEnt->MonInfo2;
 		pRADEONEnt->MonType2 = MT_NONE;
+		pRADEONEnt->MonInfo2 = NULL;
 	    } else {
 		/* Non detected, Default to a CRT connected */
 		pRADEONEnt->MonType1 = MT_CRT;
@@ -1514,7 +1515,7 @@
 		    (info->FeedbackDivider > 3)) {
 		  info->UseBiosDividers = TRUE;
 		  xf86DrvMsg(pScrn->scrnIndex, X_INFO, 
-			     "BIOS provided dividers will be used.");
+			     "BIOS provided dividers will be used.\n");
 		}
 
 		/* We don't use a while loop here just in case we have a corrupted BIOS image.
@@ -2296,6 +2297,9 @@
     val |= (Clock ? 0:RADEON_GPIO_EN_1);
     val |= (data ? 0:RADEON_GPIO_EN_0);
     OUTREG(info->DDCReg, val);
+
+    /* read back to improve reliability on some cards. */
+    val = INREG(info->DDCReg);
 }
 
 static Bool RADEONI2cInit(ScrnInfoPtr pScrn)
@@ -3995,8 +3999,9 @@
 
     if (!RADEONGetBIOSParameters(pScrn, pInt10))
 	goto fail;
-
-    RADEONGetTMDSInfo(pScrn);
+    
+    if (info->DisplayType == MT_DFP)
+	RADEONGetTMDSInfo(pScrn);
 
     if (!RADEONGetPLLParameters(pScrn))          goto fail;
 
@@ -4819,6 +4824,7 @@
     OUTREG(RADEON_CRTC_OFFSET_CNTL,     restore->crtc_offset_cntl);
     OUTREG(RADEON_CRTC_PITCH,           restore->crtc_pitch);
     OUTREG(RADEON_DISP_MERGE_CNTL,      restore->disp_merge_cntl);
+    OUTREG(RADEON_CRTC_MORE_CNTL,       restore->crtc_more_cntl);
 }
 
 /* Write CRTC2 registers */
@@ -5301,6 +5307,7 @@
     save->crtc_offset_cntl     = INREG(RADEON_CRTC_OFFSET_CNTL);
     save->crtc_pitch           = INREG(RADEON_CRTC_PITCH);
     save->disp_merge_cntl      = INREG(RADEON_DISP_MERGE_CNTL);
+    save->crtc_more_cntl       = INREG(RADEON_CRTC_MORE_CNTL);
 }
 
 /* Read flat panel registers */
@@ -6006,6 +6013,16 @@
 			  ((pScrn->bitsPerPixel * 8) -1)) /
 			 (pScrn->bitsPerPixel * 8));
     save->crtc_pitch |= save->crtc_pitch << 16;
+    
+    /* Some versions of BIOS setup CRTC_MORE_CNTL for a DFP, if we
+       have a CRT here, it should be cleared to avoild a blank screen.
+    */
+    if (info->DisplayType == MT_CRT) 
+	save->crtc_more_cntl = (info->SavedReg.crtc_more_cntl & 
+				~(RADEON_CRTC_H_CUTOFF_ACTIVE_EN |
+				  RADEON_CRTC_V_CUTOFF_ACTIVE_EN));
+    else 
+	save->crtc_more_cntl = info->SavedReg.crtc_more_cntl;
 
     save->surface_cntl = 0;
     save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
@@ -6194,16 +6211,8 @@
 
 	/* FIXME: When there are two DFPs, the 2nd DFP is driven by the
 	 *        external TMDS transmitter.  It may have a problem at
-	 *        high dot clock for certain panels.  Since we don't
-	 *        know how to control the external TMDS transmitter, not
-	 *        much we can do here.
+	 *        high dot clock for certain panels.
 	 */
-#if 0
-	if (save->dot_clock_freq > 15000)
-	    save->tmds_pll_cntl = 0xA3F;
-	else if(save->tmds_pll_cntl != 0xA3F)
-	    save->tmds_pll_cntl = info->SavedReg.tmds_pll_cntl;
-#endif
 
 	/* If BIOS has not turned it on, we'll keep it on so that we'll
 	 * have a valid VGA screen even after X quits or VT is switched
--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h.misc_orig	2003-10-03 07:28:57.000000000 -0400
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h	2003-10-03 07:39:28.000000000 -0400
@@ -298,6 +298,7 @@
 #       define RADEON_CRTC2_VSYNC_DIS       (1 << 29)
 #define RADEON_CRTC_MORE_CNTL               0x27c
 #       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)   
+#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)   
 #define RADEON_CRTC_GUI_TRIG_VLINE          0x0218
 #define RADEON_CRTC_H_SYNC_STRT_WID         0x0204
 #       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)