diff --git a/linux-core/radeon_legacy_encoders.c b/linux-core/radeon_legacy_encoders.c
index 1a1db53..76ec7a2 100644
--- a/linux-core/radeon_legacy_encoders.c
+++ b/linux-core/radeon_legacy_encoders.c
@@ -217,6 +217,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
+#if 0
 		disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
 		disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 		RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
@@ -228,9 +229,9 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 		lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 		lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 		RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
-
+#endif
 		lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
-		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
+		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN /*| RADEON_LVDS_DIGON*/ | RADEON_LVDS_BLON);
 		lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 		udelay(radeon_encoder->panel_pwr_delay * 1000);
 		RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
@@ -247,7 +248,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 		RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 		lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 		lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
-		lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
+		lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN /*| RADEON_LVDS_DIGON*/);
 		udelay(radeon_encoder->panel_pwr_delay * 1000);
 		RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 		RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
@@ -292,12 +293,13 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 
 	if (radeon_crtc->crtc_id == 0)
 		radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
-
+#if 0
 	lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 	if (radeon_encoder->lvds_gen_cntl)
 		lvds_gen_cntl = radeon_encoder->lvds_gen_cntl;
 	else
+#endif
 		lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 	lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 	lvds_gen_cntl &= ~(RADEON_LVDS_ON |
@@ -306,6 +308,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 			   RADEON_LVDS_RST_FM);
 
 	DRM_INFO("bios LVDS_GEN_CNTL: 0x%x\n", radeon_encoder->lvds_gen_cntl);
+	DRM_INFO("current LVDS_GEN_CNTL: 0x%x\n", RADEON_READ(RADEON_LVDS_GEN_CNTL));
 
 	if (radeon_is_r300(dev_priv))
 		lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
@@ -324,6 +327,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 	}
 
 	RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+#if 0
 	RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 
 	lvds_ss_gen_cntl = RADEON_READ(RADEON_LVDS_SS_GEN_CNTL);
@@ -335,7 +339,7 @@ static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 				     (radeon_encoder->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 		RADEON_WRITE(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 	}
-
+#endif
 	if (dev_priv->chip_family == CHIP_RV410)
 		RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
 }