diff --git a/src/radeon.h b/src/radeon.h index ce2fe19..eb6ea2f 100644 --- a/src/radeon.h +++ b/src/radeon.h @@ -320,6 +320,14 @@ typedef struct { CARD32 htotal_cntl2; CARD32 pixclks_cntl; + /* DDA register */ + CARD32 dda_config; + CARD32 dda_on_off; + + /* DDA2 register */ + CARD32 dda2_config; + CARD32 dda2_on_off; + /* Pallet */ Bool palette_valid; CARD32 palette[256]; @@ -350,6 +358,9 @@ typedef struct { typedef enum { CHIP_FAMILY_UNKNOW, CHIP_FAMILY_LEGACY, + CHIP_FAMILY_R128, + CHIP_FAMILY_R128PRO, + CHIP_FAMILY_R128PRO2, CHIP_FAMILY_RADEON, CHIP_FAMILY_RV100, CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ @@ -386,6 +397,10 @@ typedef enum { (info->ChipFamily == CHIP_FAMILY_RV410) || \ (info->ChipFamily == CHIP_FAMILY_RS400)) +#define IS_R128 ((info->ChipFamily == CHIP_FAMILY_R128) || \ + (info->ChipFamily == CHIP_FAMILY_R128PRO) || \ + (info->ChipFamily == CHIP_FAMILY_R128PRO2)) + /* * Errata workarounds */ @@ -406,6 +421,19 @@ typedef struct { CARD32 value; }RADEONTMDSPll; +typedef struct { /* All values in XCLKS */ + int ML; /* Memory Read Latency */ + int MB; /* Memory Burst Length */ + int Trcd; /* RAS to CAS delay */ + int Trp; /* RAS percentage */ + int Twr; /* Write Recovery */ + int CL; /* CAS Latency */ + int Tr2w; /* Read to Write Delay */ + int Rloop; /* Loop Latency */ + int Rloop_fudge; /* Add to ML to get Rloop */ + char *name; +} R128RAMRec, *R128RAMPtr; + typedef struct { EntityInfoPtr pEnt; pciVideoPtr PciInfo; @@ -823,6 +851,8 @@ typedef struct { CARD32 tv_dac_adj; + R128RAMPtr ram; + } RADEONInfoRec, *RADEONInfoPtr; #define RADEONWaitForFifo(pScrn, entries) \ diff --git a/src/radeon_driver.c b/src/radeon_driver.c index c4bda8a..ae1a033 100644 --- a/src/radeon_driver.c +++ b/src/radeon_driver.c @@ -205,6 +205,16 @@ static const OptionInfoRec RADEONOptions[] = { const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } +R128RAMRec R128RAM[] = { /* Memory Specifications + From RAGE 128 Software Development + Manual (Technical Reference Manual P/N + SDK-G04000 Rev 0.01), page 3-21. */ + { 4, 4, 3, 3, 1, 3, 1, 16, 12, "128-bit SDR SGRAM 1:1" }, + { 4, 8, 3, 3, 1, 3, 1, 17, 13, "64-bit SDR SGRAM 1:1" }, + { 4, 4, 1, 2, 1, 2, 1, 16, 12, "64-bit SDR SGRAM 2:1" }, + { 4, 4, 3, 3, 2, 3, 1, 16, 12, "64-bit DDR SGRAM" }, +}; + #ifdef WITH_VGAHW static const char *vgahwSymbols[] = { "vgaHWFreeHWRec", @@ -1052,6 +1062,9 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn) if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { pll->min_pll_freq = 20000; pll->max_pll_freq = 50000; + } else if (IS_R128) { + pll->min_pll_freq = 12500; + pll->max_pll_freq = 25000; } else { pll->min_pll_freq = 12500; pll->max_pll_freq = 35000; @@ -1322,6 +1335,45 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn) info->RamWidth /= 4; info->IsDDR = TRUE; } + } else if (IS_R128) { + switch (tmp & 0x3) { + case 0: /* SDR SGRAM 1:1 */ + switch (info->Chipset) { + case PCI_CHIP_RAGE128TF: + case PCI_CHIP_RAGE128TL: + case PCI_CHIP_RAGE128TR: + case PCI_CHIP_RAGE128LE: + case PCI_CHIP_RAGE128LF: + case PCI_CHIP_RAGE128MF: + case PCI_CHIP_RAGE128ML: + case PCI_CHIP_RAGE128RE: + case PCI_CHIP_RAGE128RF: + case PCI_CHIP_RAGE128RG: /* 128-bit SDR SGRAM 1:1 */ + info->RamWidth = 128; + info->ram = &R128RAM[0]; + break; + case PCI_CHIP_RAGE128RK: + case PCI_CHIP_RAGE128RL: + case PCI_CHIP_RAGE128SM: /* 64-bit SDR SGRAM 1:1 */ + default: + info->RamWidth = 64; + info->ram = &R128RAM[1]; + break; + } + break; + case 1: /* 64-bit SDR SGRAM 2:1 */ + info->RamWidth = 64; + info->ram = &R128RAM[2]; + break; + case 2: /* 64-bit DDR SGRAM */ + info->RamWidth = 64; + info->ram = &R128RAM[3]; + break; + default: /* 64-bit SDR SGRAM 1:1 */ + info->RamWidth = 64; + info->ram = &R128RAM[1]; + break; + } } else { if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) info->RamWidth = 128; else info->RamWidth = 64; @@ -1546,6 +1598,69 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) info->IsDellServer = FALSE; info->HasSingleDAC = FALSE; switch (info->Chipset) { + case PCI_CHIP_RAGE128RE: + case PCI_CHIP_RAGE128RF: + case PCI_CHIP_RAGE128RG: + case PCI_CHIP_RAGE128RK: + case PCI_CHIP_RAGE128RL: + case PCI_CHIP_RAGE128SM: + case PCI_CHIP_RAGE128SE: + case PCI_CHIP_RAGE128SF: + case PCI_CHIP_RAGE128SG: + case PCI_CHIP_RAGE128SH: + case PCI_CHIP_RAGE128SK: + case PCI_CHIP_RAGE128SL: + case PCI_CHIP_RAGE128SN: + info->ChipFamily = CHIP_FAMILY_R128; + pRADEONEnt->HasCRTC2 = FALSE; + break; + + case PCI_CHIP_RAGE128LE: + case PCI_CHIP_RAGE128LF: + case PCI_CHIP_RAGE128MF: + case PCI_CHIP_RAGE128ML: + info->IsMobility = TRUE; + info->ChipFamily = CHIP_FAMILY_R128PRO; + break; + + case PCI_CHIP_RAGE128PA: + case PCI_CHIP_RAGE128PB: + case PCI_CHIP_RAGE128PC: + case PCI_CHIP_RAGE128PE: + case PCI_CHIP_RAGE128PG: + case PCI_CHIP_RAGE128PH: + case PCI_CHIP_RAGE128PI: + case PCI_CHIP_RAGE128PJ: + case PCI_CHIP_RAGE128PK: + case PCI_CHIP_RAGE128PL: + case PCI_CHIP_RAGE128PM: + case PCI_CHIP_RAGE128PN: + case PCI_CHIP_RAGE128PO: + case PCI_CHIP_RAGE128PQ: + case PCI_CHIP_RAGE128PS: + case PCI_CHIP_RAGE128PT: + case PCI_CHIP_RAGE128PU: + case PCI_CHIP_RAGE128PV: + case PCI_CHIP_RAGE128PW: + case PCI_CHIP_RAGE128PX: + case PCI_CHIP_RAGE128PD: + case PCI_CHIP_RAGE128PF: + case PCI_CHIP_RAGE128PP: + case PCI_CHIP_RAGE128PR: + info->ChipFamily = CHIP_FAMILY_R128PRO; + pRADEONEnt->HasCRTC2 = FALSE; + break; + + case PCI_CHIP_RAGE128TF: + case PCI_CHIP_RAGE128TL: + case PCI_CHIP_RAGE128TR: + case PCI_CHIP_RAGE128TS: + case PCI_CHIP_RAGE128TT: + case PCI_CHIP_RAGE128TU: + info->ChipFamily = CHIP_FAMILY_R128PRO2; + pRADEONEnt->HasCRTC2 = FALSE; + break; + case PCI_CHIP_RADEON_LY: case PCI_CHIP_RADEON_LZ: info->IsMobility = TRUE; @@ -4629,6 +4744,26 @@ static void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, } +/* Write DDA registers. */ +static void R128RestoreDDARegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + OUTREG(R128_DDA_CONFIG, restore->dda_config); + OUTREG(R128_DDA_ON_OFF, restore->dda_on_off); +} + +/* Write DDA registers. */ +static void R128RestoreDDA2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + OUTREG(R128_DDA2_CONFIG, restore->dda2_config); + OUTREG(R128_DDA2_ON_OFF, restore->dda2_on_off); +} + /* Write flat panel registers */ static void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) { @@ -5116,6 +5251,8 @@ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) if (info->IsSecondary) { RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCommonRegisters(pScrn, restore); + if (IS_R128) + R128RestoreDDA2Registers(pScrn, restore); RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); @@ -5128,10 +5265,14 @@ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCommonRegisters(pScrn, restore); if (pCRTC2->binding == 1) { + if (IS_R128) + R128RestoreDDA2Registers(pScrn, restore); RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); } + if (IS_R128) + R128RestoreDDARegisters(pScrn, restore); RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestorePLLRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); @@ -5152,10 +5293,14 @@ static void RADEONRestoreMode(ScrnInfoPtr pScrn, RADEONSavePtr restore) RADEONRestoreMemMapRegisters(pScrn, restore); RADEONRestoreCommonRegisters(pScrn, restore); if ((pCRTC2->binding == 1) || pRADEONEnt->HasSecondary) { + if (IS_R128) + R128RestoreDDA2Registers(pScrn, restore); RADEONRestoreCrtc2Registers(pScrn, restore); RADEONRestorePLL2Registers(pScrn, restore); } + if (IS_R128) + R128RestoreDDARegisters(pScrn, restore); RADEONRestoreCrtcRegisters(pScrn, restore); RADEONRestorePLLRegisters(pScrn, restore); RADEONRestoreFPRegisters(pScrn, restore); @@ -5320,6 +5465,26 @@ static void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); } +/* Read DDA registers. */ +static void R128SaveDDARegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + save->dda_config = INREG(R128_DDA_CONFIG); + save->dda_on_off = INREG(R128_DDA_ON_OFF); +} + +/* Read DDA2 registers. */ +static void R128SaveDDA2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) +{ + RADEONInfoPtr info = RADEONPTR(pScrn); + unsigned char *RADEONMMIO = info->MMIO; + + save->dda2_config = INREG(R128_DDA2_CONFIG); + save->dda2_on_off = INREG(R128_DDA2_ON_OFF); +} + /* Read PLL registers */ static void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) { @@ -5391,6 +5556,10 @@ static void RADEONSaveMode(ScrnInfoPtr pScrn, RADEONSavePtr save) RADEONSaveMemMapRegisters(pScrn, save); RADEONSaveCommonRegisters(pScrn, save); RADEONSavePLLRegisters (pScrn, save); + if (IS_R128) { + R128SaveDDARegisters(pScrn, save); + R128SaveDDA2Registers(pScrn, save); + } RADEONSaveCrtcRegisters (pScrn, save); RADEONSaveFPRegisters (pScrn, save); RADEONSaveCrtc2Registers (pScrn, save); @@ -5862,6 +6031,155 @@ static void RADEONInitOutputRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, Dis } } +/* Define DDA registers for requested video mode. */ +static Bool R128InitDDARegisters(ScrnInfoPtr pScrn, RADEONInfoPtr info, + RADEONSavePtr save, RADEONPLLPtr pll, + DisplayModePtr mode) +{ + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + int DisplayFifoWidth = 128; + int DisplayFifoDepth = 32; + int XclkFreq; + int VclkFreq; + int XclksPerTransfer; + int XclksPerTransferPrecise; + int UseablePrecision; + int Roff; + int Ron; + + XclkFreq = pll->xclk; + + VclkFreq = R128Div(pll->reference_freq * save->feedback_div, + pll->reference_div * save->post_div); + +#if 1 + if (pRADEONEnt->PortInfo[0]->MonType == MT_LCD || + pRADEONEnt->PortInfo[0]->MonType == MT_DFP /*&& !info->isPro2*/){ + if (info->PanelXRes != mode->CrtcHDisplay) + VclkFreq = (VclkFreq * mode->CrtcHDisplay) / info->PanelXRes; + } +#endif + + XclksPerTransfer = RADEONDiv(XclkFreq * DisplayFifoWidth, + VclkFreq * (info->CurrentLayout.pixel_bytes * 8)); + + UseablePrecision = RADEONMinBits(XclksPerTransfer) + 1; + + XclksPerTransferPrecise = RADEONDiv((XclkFreq * DisplayFifoWidth) + << (11 - UseablePrecision), + VclkFreq * (info->CurrentLayout.pixel_bytes * 8)); + + Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4); + + Ron = (4 * info->ram->MB + + 3 * MAX(info->ram->Trcd - 2, 0) + + 2 * info->ram->Trp + + info->ram->Twr + + info->ram->CL + + info->ram->Tr2w + + XclksPerTransfer) << (11 - UseablePrecision); + + if (Ron + info->ram->Rloop >= Roff) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n", + Ron, info->ram->Rloop, Roff); + return FALSE; + } + + save->dda_config = (XclksPerTransferPrecise + | (UseablePrecision << 16) + | (info->ram->Rloop << 20)); + + save->dda_on_off = (Ron << 16) | Roff; + + RADEONTRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n", + XclkFreq, + VclkFreq, + XclksPerTransfer, + XclksPerTransferPrecise, + UseablePrecision)); + RADEONTRACE(("Roff = %d, Ron = %d, Rloop = %d\n", + Roff, Ron, info->ram->Rloop)); + + return TRUE; +} + +/* Define DDA2 registers for requested video mode. */ +static Bool R128InitDDA2Registers(ScrnInfoPtr pScrn, RADEONInfoPtr info, + RADEONSavePtr save, RADEONPLLPtr pll, + DisplayModePtr mode) +{ + RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); + int DisplayFifoWidth = 128; + int DisplayFifoDepth = 32; + int XclkFreq; + int VclkFreq; + int XclksPerTransfer; + int XclksPerTransferPrecise; + int UseablePrecision; + int Roff; + int Ron; + + XclkFreq = pll->xclk; + + VclkFreq = RADEONDiv(pll->reference_freq * save->feedback_div_2, + pll->reference_div * save->post_div_2); +#if 1 + if (pRADEONEnt->PortInfo[1]->MonType == MT_LCD || + pRADEONEnt->PortInfo[1]->MonType == MT_DFP /*&& !info->isPro2*/) { + if (info->PanelXRes != mode->CrtcHDisplay) + VclkFreq = (VclkFreq * mode->CrtcHDisplay) / info->PanelXRes; + } +#endif + + XclksPerTransfer = RADEONDiv(XclkFreq * DisplayFifoWidth, + VclkFreq * (info->CurrentLayout.pixel_bytes * 8)); + + UseablePrecision = RADEONMinBits(XclksPerTransfer) + 1; + + XclksPerTransferPrecise = RADEONDiv((XclkFreq * DisplayFifoWidth) + << (11 - UseablePrecision), + VclkFreq * (info->CurrentLayout.pixel_bytes * 8)); + + Roff = XclksPerTransferPrecise * (DisplayFifoDepth - 4); + + Ron = (4 * info->ram->MB + + 3 * MAX(info->ram->Trcd - 2, 0) + + 2 * info->ram->Trp + + info->ram->Twr + + info->ram->CL + + info->ram->Tr2w + + XclksPerTransfer) << (11 - UseablePrecision); + + + if (Ron + info->ram->Rloop >= Roff) { + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "(Ron = %d) + (Rloop = %d) >= (Roff = %d)\n", + Ron, info->ram->Rloop, Roff); + return FALSE; + } + + save->dda2_config = (XclksPerTransferPrecise + | (UseablePrecision << 16) + | (info->ram->Rloop << 20)); + + /*save->dda2_on_off = (Ron << 16) | Roff;*/ + /* shift most be 18 otherwise there's corruption on crtc2 */ + save->dda2_on_off = (Ron << 18) | Roff; + + RADEONTRACE(("XclkFreq = %d; VclkFreq = %d; per = %d, %d (useable = %d)\n", + XclkFreq, + VclkFreq, + XclksPerTransfer, + XclksPerTransferPrecise, + UseablePrecision)); + RADEONTRACE(("Roff = %d, Ron = %d, Rloop = %d\n", + Roff, Ron, info->ram->Rloop)); + + return TRUE; +} + + /* Define CRTC registers for requested video mode */ static Bool RADEONInitCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, DisplayModePtr mode, RADEONInfoPtr info) @@ -6417,6 +6735,8 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, save->ppll_div_3 = info->SavedReg.ppll_div_3; save->htotal_cntl = info->SavedReg.htotal_cntl; } + if (IS_R128) + R128InitDDARegisters(pScrn, info, save, &info->pll, crtc1); if (pRADEONEnt->HasSecondary) { pScrn0 = pRADEONEnt->pSecondaryScrn; info0 = RADEONPTR(pScrn0); @@ -6434,6 +6754,8 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, if (!RADEONInitCrtc2Registers(pScrn, save, crtc2, info)) return FALSE; RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->DisplayType != MT_CRT); + if (IS_R128) + R128InitDDA2Registers(pScrn, info, save, &info->pll, crtc2); /* Make sure primary has the same copy */ memcpy(&info0->ModeReg, save, sizeof(RADEONSaveRec)); break; @@ -6449,9 +6771,13 @@ static Bool RADEONInit2(ScrnInfoPtr pScrn, DisplayModePtr crtc1, save->ppll_div_3 = info->SavedReg.ppll_div_3; save->htotal_cntl = info->SavedReg.htotal_cntl; } + if (IS_R128) + R128InitDDARegisters(pScrn, info, save, &info->pll, crtc1); RADEONInitCrtc2Registers(pScrn, save, crtc2, info); dot_clock = crtc2->Clock / 1000.0; RADEONInitPLL2Registers(pScrn, save, &info->pll, dot_clock, info->MergeType != MT_CRT); + if (IS_R128) + R128InitDDA2Registers(pScrn, info, save, &info->pll, crtc2); break; default: return FALSE; diff --git a/src/radeon_probe.c b/src/radeon_probe.c index d7ff643..1532d34 100644 --- a/src/radeon_probe.c +++ b/src/radeon_probe.c @@ -54,6 +54,55 @@ #include "radeon_chipset.h" PciChipsets RADEONPciChipsets[] = { + /* r128 */ + { PCI_CHIP_RAGE128LE, PCI_CHIP_RAGE128LE, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128LF, PCI_CHIP_RAGE128LF, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128MF, PCI_CHIP_RAGE128MF, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128ML, PCI_CHIP_RAGE128ML, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PA, PCI_CHIP_RAGE128PA, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PB, PCI_CHIP_RAGE128PB, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PC, PCI_CHIP_RAGE128PC, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PD, PCI_CHIP_RAGE128PD, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PE, PCI_CHIP_RAGE128PE, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PF, PCI_CHIP_RAGE128PF, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PG, PCI_CHIP_RAGE128PG, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PH, PCI_CHIP_RAGE128PH, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PI, PCI_CHIP_RAGE128PI, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PJ, PCI_CHIP_RAGE128PJ, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PK, PCI_CHIP_RAGE128PK, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PL, PCI_CHIP_RAGE128PL, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PM, PCI_CHIP_RAGE128PM, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PN, PCI_CHIP_RAGE128PN, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PO, PCI_CHIP_RAGE128PO, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PP, PCI_CHIP_RAGE128PP, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PQ, PCI_CHIP_RAGE128PQ, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PR, PCI_CHIP_RAGE128PR, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PS, PCI_CHIP_RAGE128PS, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PT, PCI_CHIP_RAGE128PT, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PU, PCI_CHIP_RAGE128PU, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PV, PCI_CHIP_RAGE128PV, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PW, PCI_CHIP_RAGE128PW, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128PX, PCI_CHIP_RAGE128PX, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128RE, PCI_CHIP_RAGE128RE, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128RF, PCI_CHIP_RAGE128RF, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128RG, PCI_CHIP_RAGE128RG, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128RK, PCI_CHIP_RAGE128RK, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128RL, PCI_CHIP_RAGE128RL, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SE, PCI_CHIP_RAGE128SE, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SF, PCI_CHIP_RAGE128SF, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SG, PCI_CHIP_RAGE128SG, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SH, PCI_CHIP_RAGE128SH, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SK, PCI_CHIP_RAGE128SK, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SL, PCI_CHIP_RAGE128SL, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SM, PCI_CHIP_RAGE128SM, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128SN, PCI_CHIP_RAGE128SN, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128TF, PCI_CHIP_RAGE128TF, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128TL, PCI_CHIP_RAGE128TL, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128TR, PCI_CHIP_RAGE128TR, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128TS, PCI_CHIP_RAGE128TS, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128TT, PCI_CHIP_RAGE128TT, RES_SHARED_VGA }, + { PCI_CHIP_RAGE128TU, PCI_CHIP_RAGE128TU, RES_SHARED_VGA }, + /* radeon */ { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, diff --git a/src/radeon_reg.h b/src/radeon_reg.h index b50fcf0..f17490e 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -449,6 +449,11 @@ #define RADEON_CUR2_OFFSET 0x0360 # define RADEON_CUR2_LOCK (1 << 31) +#define R128_DDA_CONFIG 0x02e0 +#define R128_DDA_ON_OFF 0x02e4 +#define R128_DDA2_CONFIG 0x03e0 +#define R128_DDA2_ON_OFF 0x03e4 + #define RADEON_DAC_CNTL 0x0058 # define RADEON_DAC_RANGE_CNTL (3 << 0) # define RADEON_DAC_RANGE_CNTL_MASK 0x03