diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c index 8f5b40a..02d3f66 100644 --- a/src/atombios_crtc.c +++ b/src/atombios_crtc.c @@ -200,6 +200,37 @@ atombios_set_crtc_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_TIMING_PARAMETERS_ return ATOM_NOT_IMPLEMENTED; } +static AtomBiosResult +atombios_set_crtc_dtd_timing(atomBiosHandlePtr atomBIOS, SET_CRTC_USING_DTD_TIMING_PARAMETERS *crtc_param) +{ + AtomBiosArgRec data; + unsigned char *space; + SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; + + conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); + conv_param.usH_Blanking_Time = cpu_to_le16(crtc_param->usH_Blanking_Time); + conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); + conv_param.usV_Blanking_Time = cpu_to_le16(crtc_param->usV_Blanking_Time); + conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); + conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); + conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); + conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); + conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); + conv_param.ucCRTC = crtc_param->ucCRTC; + + data.exec.index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); + data.exec.dataSpace = (void *)&space; + data.exec.pspace = &conv_param; + + if (RHDAtomBiosFunc(atomBIOS->scrnIndex, atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) { + ErrorF("Set DTD CRTC Timing success\n"); + return ATOM_SUCCESS ; + } + + ErrorF("Set DTD CRTC Timing failed\n"); + return ATOM_NOT_IMPLEMENTED; +} + void atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) { @@ -221,19 +252,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) AtomBiosArgRec data; unsigned char *space; RADEONSavePtr save = info->ModeReg; + uint32_t temp; if (IS_AVIVO_VARIANT) { - uint32_t temp; - - if (mode->Clock > 120000) /* range limits??? */ - pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; - else - pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; - - - RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); - sclock = temp; - /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ if (radeon_crtc->crtc_id == 0) { temp = INREG(AVIVO_P1PLL_INT_SS_CNTL); @@ -242,12 +263,16 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode, int pll_flags) temp = INREG(AVIVO_P2PLL_INT_SS_CNTL); OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1); } - } else { - sclock = save->dot_clock_freq; - fb_div = save->feedback_div; - post_div = save->post_div; - ref_div = save->ppll_ref_div; - } + } else + pll_flags |= RADEON_PLL_LEGACY; + + if (mode->Clock > 120000) /* range limits??? */ + pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; + else + pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; + + RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags); + sclock = temp; xf86DrvMsg(crtc->scrn->scrnIndex, X_INFO, "crtc(%d) Clock: mode %d, PLL %lu\n", @@ -374,9 +399,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, int need_tv_timings = 0; int i, ret; SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; + SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; Bool tilingChanged = FALSE; int pll_flags = 0; memset(&crtc_timing, 0, sizeof(crtc_timing)); + memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing)); if (info->allowColorTiling) { radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; @@ -442,6 +469,34 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, if (adjusted_mode->Flags & V_DBLSCAN) crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; + crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id; + crtc_dtd_timing.usH_Size = adjusted_mode->CrtcHDisplay; + crtc_dtd_timing.usV_Size = adjusted_mode->CrtcVDisplay; + crtc_dtd_timing.usH_Blanking_Time = adjusted_mode->CrtcHBlankEnd - adjusted_mode->CrtcHDisplay; + crtc_dtd_timing.usV_Blanking_Time = adjusted_mode->CrtcVBlankEnd - adjusted_mode->CrtcVDisplay; + crtc_dtd_timing.usH_SyncOffset = adjusted_mode->CrtcHSyncStart - adjusted_mode->CrtcHDisplay; + crtc_dtd_timing.usV_SyncOffset = adjusted_mode->CrtcVSyncStart - adjusted_mode->CrtcVDisplay; + crtc_dtd_timing.usH_SyncWidth = adjusted_mode->CrtcHSyncEnd - adjusted_mode->CrtcHSyncStart; + crtc_dtd_timing.usV_SyncWidth = adjusted_mode->CrtcVSyncEnd - adjusted_mode->CrtcVSyncStart; + ErrorF("%d %d %d %d %d %d %d %d\n", crtc_dtd_timing.usH_Size, crtc_dtd_timing.usH_SyncOffset, + crtc_dtd_timing.usH_SyncWidth, crtc_dtd_timing.usH_Blanking_Time, + crtc_dtd_timing.usV_Size, crtc_dtd_timing.usV_SyncOffset, + crtc_dtd_timing.usV_SyncWidth, crtc_dtd_timing.usV_Blanking_Time); + + if (adjusted_mode->Flags & V_NVSYNC) + crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; + + if (adjusted_mode->Flags & V_NHSYNC) + crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; + + if (adjusted_mode->Flags & V_CSYNC) + crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; + + if (adjusted_mode->Flags & V_INTERLACE) + crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; + + if (adjusted_mode->Flags & V_DBLSCAN) + crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; } ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay, @@ -450,6 +505,12 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); + atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags); + atombios_set_crtc_timing(info->atomBIOS, &crtc_timing); + // setup FP shadow timing regs on ry4xx + if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0)) + atombios_set_crtc_dtd_timing(info->atomBIOS, &crtc_dtd_timing); + if (IS_AVIVO_VARIANT) { uint32_t fb_format; @@ -512,15 +573,66 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, else OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); - } - - atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags); + } else { + int format; + uint32_t crtc_gen_cntl, crtc2_gen_cntl; + + ErrorF("init common\n"); + RADEONInitCommonRegisters(info->ModeReg, info); + RADEONInitSurfaceCntl(crtc, info->ModeReg); + ErrorF("restore common\n"); + RADEONRestoreCommonRegisters(pScrn, info->ModeReg); + + switch (info->CurrentLayout.pixel_code) { + case 4: format = 1; break; + case 8: format = 2; break; + case 15: format = 3; break; /* 555 */ + case 16: format = 4; break; /* 565 */ + case 24: format = 5; break; /* RGB */ + case 32: format = 6; break; /* xRGB */ + default: + xf86DrvMsg(pScrn->scrnIndex, X_ERROR, + "Unsupported pixel depth (%d)\n", + info->CurrentLayout.bitsPerPixel); + } - atombios_set_crtc_timing(info->atomBIOS, &crtc_timing); + switch (radeon_crtc->crtc_id) { + case 0: + ErrorF("init crtc1\n"); + crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff; + crtc_gen_cntl |= (format << 8); + OUTREG(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); + RADEONInitCrtcBase(crtc, info->ModeReg, x, y); + if (IS_R300_VARIANT) + OUTREG(R300_CRTC_TILE_X0_Y0, info->ModeReg->crtc_tile_x0_y0); + OUTREG(RADEON_CRTC_OFFSET_CNTL, info->ModeReg->crtc_offset_cntl); + OUTREG(RADEON_CRTC_OFFSET, info->ModeReg->crtc_offset); + OUTREG(RADEON_CRTC_PITCH, info->ModeReg->crtc_pitch); + //OUTREG(RADEON_FP_H_SYNC_STRT_WID, INREG(RADEON_CRTC_H_SYNC_STRT_WID)); + //OUTREG(RADEON_FP_V_SYNC_STRT_WID, INREG(RADEON_CRTC_V_SYNC_STRT_WID)); + //OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, INREG(RADEON_CRTC_H_TOTAL_DISP)); + //OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, INREG(RADEON_CRTC_V_TOTAL_DISP)); + break; + case 1: + ErrorF("init crtc2\n"); + crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff; + crtc2_gen_cntl |= (format << 8); + OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); + RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); + if (IS_R300_VARIANT) + OUTREG(R300_CRTC2_TILE_X0_Y0, info->ModeReg->crtc2_tile_x0_y0); + OUTREG(RADEON_CRTC2_OFFSET_CNTL, info->ModeReg->crtc2_offset_cntl); + OUTREG(RADEON_CRTC2_OFFSET, info->ModeReg->crtc2_offset); + OUTREG(RADEON_CRTC2_PITCH, info->ModeReg->crtc2_pitch); + //OUTREG(RADEON_FP_H2_SYNC_STRT_WID, INREG(RADEON_CRTC2_H_SYNC_STRT_WID)); + //OUTREG(RADEON_FP_V2_SYNC_STRT_WID, INREG(RADEON_CRTC2_V_SYNC_STRT_WID)); + break; + } + } if (info->DispPriority) RADEONInitDispBandwidth(pScrn); - +#if 1 if (tilingChanged) { /* need to redraw front buffer, I guess this can be considered a hack ? */ /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ @@ -531,7 +643,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc, xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE); /* xf86SetRootClip would do, but can't access that here */ } - +#endif } /* Calculate display buffer watermark to prevent buffer underflow */ diff --git a/src/atombios_output.c b/src/atombios_output.c index 83b86a7..a669616 100644 --- a/src/atombios_output.c +++ b/src/atombios_output.c @@ -573,6 +573,9 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) AtomBiosArgRec data; unsigned char *space; + if (!IS_AVIVO_VARIANT && radeon_crtc->crtc_id) + return ATOM_SUCCESS; + disp_data.ucScaler = radeon_crtc->crtc_id; if (radeon_output->Flags & RADEON_USE_RMX) { @@ -583,7 +586,10 @@ atombios_output_scaler_setup(xf86OutputPtr output, DisplayModePtr mode) disp_data.ucEnable = ATOM_SCALER_CENTER; } else { ErrorF("Not using RMX\n"); - disp_data.ucEnable = ATOM_SCALER_DISABLE; + if (IS_AVIVO_VARIANT) + disp_data.ucEnable = ATOM_SCALER_DISABLE; + else + disp_data.ucEnable = ATOM_SCALER_CENTER; } data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableScaler); @@ -606,6 +612,9 @@ dfp_disable_dither(xf86OutputPtr output, int device) RADEONInfoPtr info = RADEONPTR(output->scrn); unsigned char *RADEONMMIO = info->MMIO; + if (!IS_AVIVO_VARIANT) + return; + switch (device) { case ATOM_DEVICE_DFP1_SUPPORT: OUTREG(AVIVO_TMDSA_BIT_DEPTH_CONTROL, 0); /* TMDSA */ @@ -968,7 +977,7 @@ atombios_output_mode_set(xf86OutputPtr output, } static AtomBiosResult -atom_bios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) +atombios_dac_load_detect(atomBiosHandlePtr atomBIOS, xf86OutputPtr output) { RADEONOutputPrivatePtr radeon_output = output->driver_private; RADEONInfoPtr info = RADEONPTR(output->scrn); @@ -1045,7 +1054,7 @@ atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output) } } - ret = atom_bios_dac_load_detect(info->atomBIOS, output); + ret = atombios_dac_load_detect(info->atomBIOS, output); if (ret == ATOM_SUCCESS) { if (info->ChipFamily >= CHIP_FAMILY_R600) bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index 8995679..4cee0ed 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -691,7 +691,7 @@ legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) /* Define common registers for requested video mode */ -static void +void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) { save->ovr_clr = 0; @@ -722,7 +722,7 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; } -static void +void RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) { save->surface_cntl = 0; @@ -747,7 +747,7 @@ RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) } -static Bool +Bool RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, int x, int y) { @@ -759,6 +759,11 @@ RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, XF86DRISAREAPtr pSAREA; #endif + save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + + ((pScrn->bitsPerPixel * 8) -1)) / + (pScrn->bitsPerPixel * 8)); + save->crtc_pitch |= save->crtc_pitch << 16; + save->crtc_offset = pScrn->fbOffset; #ifdef XF86DRI if (info->allowPageFlip) @@ -939,11 +944,6 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, ? RADEON_CRTC_V_SYNC_POL : 0)); - save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + - ((pScrn->bitsPerPixel * 8) -1)) / - (pScrn->bitsPerPixel * 8)); - save->crtc_pitch |= save->crtc_pitch << 16; - if (info->IsDellServer) { save->dac2_cntl = info->SavedReg->dac2_cntl; save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; @@ -964,8 +964,7 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, return TRUE; } - -static Bool +Bool RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, int x, int y) { @@ -977,6 +976,10 @@ RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, XF86DRISAREAPtr pSAREA; #endif + save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + + ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); + save->crtc2_pitch |= save->crtc2_pitch << 16; + /* It seems all fancy options apart from pflip can be safely disabled */ save->crtc2_offset = pScrn->fbOffset; @@ -1131,10 +1134,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, ? RADEON_CRTC2_V_SYNC_POL : 0)); - save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + - ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); - save->crtc2_pitch |= save->crtc2_pitch << 16; - /* check to see if TV DAC is enabled for another crtc and keep it enabled */ if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON) save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c index f0a3a31..866c967 100644 --- a/src/radeon_atombios.c +++ b/src/radeon_atombios.c @@ -2033,7 +2033,7 @@ CailDelayMicroSeconds(VOID *CAIL, UINT32 delay) usleep(delay); - /*DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay));*/ + DEBUGP(xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_INFO,"Delay %i usec\n",delay)); } UINT32 @@ -2046,7 +2046,7 @@ CailReadATIRegister(VOID* CAIL, UINT32 idx) CAILFUNC(CAIL); ret = INREG(idx << 2); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret));*/ + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx << 2,ret)); return ret; } @@ -2059,7 +2059,7 @@ CailWriteATIRegister(VOID *CAIL, UINT32 idx, UINT32 data) CAILFUNC(CAIL); OUTREG(idx << 2,data); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data));*/ + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx << 2,data)); } UINT32 @@ -2074,10 +2074,10 @@ CailReadFBData(VOID* CAIL, UINT32 idx) if (((atomBiosHandlePtr)CAIL)->fbBase) { uint8_t *FBBase = (uint8_t*)info->FB; ret = *((uint32_t*)(FBBase + (((atomBiosHandlePtr)CAIL)->fbBase) + idx)); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); } else if (((atomBiosHandlePtr)CAIL)->scratchBase) { ret = *(uint32_t*)((uint8_t*)(((atomBiosHandlePtr)CAIL)->scratchBase) + idx); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret));*/ + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,ret)); } else { xf86DrvMsg(((atomBiosHandlePtr)CAIL)->scrnIndex,X_ERROR, "%s: no fbbase set\n",__func__); @@ -2091,7 +2091,7 @@ CailWriteFBData(VOID *CAIL, UINT32 idx, UINT32 data) { CAILFUNC(CAIL); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data));*/ + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,data)); if (((atomBiosHandlePtr)CAIL)->fbBase) { uint8_t *FBBase = (uint8_t*) RADEONPTR(xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex])->FB; @@ -2112,7 +2112,7 @@ CailReadMC(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = INMC(pScrn, Address); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));*/ + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); return ret; } @@ -2122,7 +2122,7 @@ CailWriteMC(VOID *CAIL, ULONG Address, ULONG data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data));*/ + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,data)); OUTMC(pScrn, Address, data); } @@ -2168,7 +2168,7 @@ CailReadPCIConfigData(VOID*CAIL, VOID* ret, UINT32 idx,UINT16 size) return; break; } - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret));*/ + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,idx,*(unsigned int*)ret)); } @@ -2178,7 +2178,7 @@ CailWritePCIConfigData(VOID*CAIL,VOID*src,UINT32 idx,UINT16 size) PCITAG tag = ((atomBiosHandlePtr)CAIL)->PciTag; CAILFUNC(CAIL); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src)));*/ + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,idx,(*(unsigned int*)src))); switch (size) { case 8: pciWriteByte(tag,idx << 2,*(uint8_t*)src); @@ -2206,7 +2206,7 @@ CailReadPLL(VOID *CAIL, ULONG Address) CAILFUNC(CAIL); ret = RADEONINPLL(pScrn, Address); - /*DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret));*/ + DEBUGP(ErrorF("%s(%x) = %x\n",__func__,Address,ret)); return ret; } @@ -2216,7 +2216,7 @@ CailWritePLL(VOID *CAIL, ULONG Address,ULONG Data) ScrnInfoPtr pScrn = xf86Screens[((atomBiosHandlePtr)CAIL)->scrnIndex]; CAILFUNC(CAIL); - /*DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data));*/ + DEBUGP(ErrorF("%s(%x,%x)\n",__func__,Address,Data)); RADEONOUTPLL(pScrn, Address, Data); } diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c index 5ab00c1..0906e66 100644 --- a/src/radeon_crtc.c +++ b/src/radeon_crtc.c @@ -78,7 +78,7 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode) if ((mode == DPMSModeOn) && radeon_crtc->enabled) return; - if (IS_AVIVO_VARIANT) { + if (info->IsAtomBios) { atombios_crtc_dpms(crtc, mode); } else { @@ -272,7 +272,7 @@ radeon_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, ScrnInfoPtr pScrn = crtc->scrn; RADEONInfoPtr info = RADEONPTR(pScrn); - if (IS_AVIVO_VARIANT) { + if (info->IsAtomBios) { atombios_crtc_mode_set(crtc, mode, adjusted_mode, x, y); } else { legacy_crtc_mode_set(crtc, mode, adjusted_mode, x, y); diff --git a/src/radeon_output.c b/src/radeon_output.c index 7d7f88a..265da8a 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -350,7 +350,7 @@ radeon_dpms(xf86OutputPtr output, int mode) if ((mode == DPMSModeOn) && radeon_output->enabled) return; - if (IS_AVIVO_VARIANT) { + if (info->IsAtomBios) { atombios_output_dpms(output, mode); } else { legacy_output_dpms(output, mode); @@ -527,7 +527,7 @@ radeon_mode_prepare(xf86OutputPtr output) RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; if (other_crtc->enabled) { radeon_crtc_dpms(other_crtc, DPMSModeOff); - if (IS_AVIVO_VARIANT) + if (info->IsAtomBios) atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 1); radeon_dpms(loop_output, DPMSModeOff); } @@ -546,7 +546,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode, { RADEONInfoPtr info = RADEONPTR(output->scrn); - if (IS_AVIVO_VARIANT) + if (info->IsAtomBios) atombios_output_mode_set(output, mode, adjusted_mode); else legacy_output_mode_set(output, mode, adjusted_mode); @@ -570,7 +570,7 @@ radeon_mode_commit(xf86OutputPtr output) RADEONCrtcPrivatePtr other_radeon_crtc = other_crtc->driver_private; if (other_crtc->enabled) { radeon_crtc_dpms(other_crtc, DPMSModeOn); - if (IS_AVIVO_VARIANT) + if (info->IsAtomBios) atombios_lock_crtc(info->atomBIOS, other_radeon_crtc->crtc_id, 0); radeon_dpms(loop_output, DPMSModeOn); }