diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index dba197e..c7d42bc 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -496,44 +496,9 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	}
 	FINISH_ACCEL();
 
-	/* pre-load FS tex instructions */
-	if (IS_R300_3D) {
-	    BEGIN_ACCEL(2);
-	    /* tex inst for src texture */
-	    OUT_ACCEL_REG(R300_US_TEX_INST(0),
-			  (R300_TEX_SRC_ADDR(0) |
-			   R300_TEX_DST_ADDR(0) |
-			   R300_TEX_ID(0) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-
-	    /* tex inst for mask texture */
-	    OUT_ACCEL_REG(R300_US_TEX_INST(1),
-			  (R300_TEX_SRC_ADDR(1) |
-			   R300_TEX_DST_ADDR(1) |
-			   R300_TEX_ID(1) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-	    FINISH_ACCEL();
-	}
-
-	if (IS_R300_3D) {
-	    BEGIN_ACCEL(8);
-	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	} else {
+	if (IS_R300_3D)
+	    BEGIN_ACCEL(4);
+	else {
 	    BEGIN_ACCEL(6);
 	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
 	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index e5cc196..f225adc 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1422,8 +1422,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 
 
 	/* setup the rasterizer, load FS */
-	BEGIN_ACCEL(10);
 	if (pMask) {
+	    BEGIN_ACCEL(16);
 	    /* 4 components: 2 for tex0, 2 for tex1 */
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1443,7 +1443,10 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 			   R300_TEX_START(0) |
 			   R300_TEX_SIZE(1) |
 			   R300_RGBA_OUT));
+
+
 	} else {
+	    BEGIN_ACCEL(15);
 	    /* 2 components: 2 for tex0 */
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -1462,14 +1465,45 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 			   R300_TEX_START(0) |
 			   R300_TEX_SIZE(0) |
 			   R300_RGBA_OUT));
+
 	}
 
+	OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
+		      (R300_ALU_START(0) |
+		       R300_ALU_SIZE(0) |
+		       R300_TEX_START(0) |
+		       R300_TEX_SIZE(0)));
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
+		      (R300_ALU_START(0) |
+		       R300_ALU_SIZE(0) |
+		       R300_TEX_START(0) |
+		       R300_TEX_SIZE(0)));
+	OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
+		      (R300_ALU_START(0) |
+		       R300_ALU_SIZE(0) |
+		       R300_TEX_START(0) |
+		       R300_TEX_SIZE(0)));
+
 	OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
 	/* shader output swizzling */
 	OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
 
-	/* tex inst for src texture is pre-loaded in RADEONInit3DEngine() */
-	/* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */
+	/* tex inst for src texture */
+	OUT_ACCEL_REG(R300_US_TEX_INST(0),
+		      (R300_TEX_SRC_ADDR(0) |
+		       R300_TEX_DST_ADDR(0) |
+		       R300_TEX_ID(0) |
+		       R300_TEX_INST(R300_TEX_INST_LD)));
+
+	if (pMask) {
+	    /* tex inst for mask texture */
+	    OUT_ACCEL_REG(R300_US_TEX_INST(1),
+			  (R300_TEX_SRC_ADDR(1) |
+			   R300_TEX_DST_ADDR(1) |
+			   R300_TEX_ID(1) |
+			   R300_TEX_INST(R300_TEX_INST_LD)));
+	}
 
 	/* RGB inst
 	 * temp addresses for texture inputs
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 6a66335..df04512 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -432,7 +432,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 						   R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0)));
 		OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(1), (R300_ALU_ALPHA_ADDRD(3) |
 						   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_NONE)));
-		
+
 
 		/* MUL temp2.rg, temp2.rrr0, const0.rgb */
 		OUT_ACCEL_REG(R300_US_ALU_RGB_INST(2), (R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |