diff --git a/shared-core/drm_pciids.txt b/shared-core/drm_pciids.txt index 6c93abe..fdcd6be 100644 --- a/shared-core/drm_pciids.txt +++ b/shared-core/drm_pciids.txt @@ -250,6 +250,11 @@ 0x1002 0x940A CHIP_R600|RADEON_NEW_MEMMAP "ATI FireGL V8650" 0x1002 0x940B CHIP_R600|RADEON_NEW_MEMMAP "ATI FireGL V8600" 0x1002 0x940F CHIP_R600|RADEON_NEW_MEMMAP "ATI FireGL V7600" +0x1002 0x94A0 CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4830" +0x1002 0x94A1 CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP "ATI Mobility Radeon HD 4850" +0x1002 0x94B1 CHIP_RV740|RADEON_NEW_MEMMAP "ATI RV740" +0x1002 0x94B3 CHIP_RV740|RADEON_NEW_MEMMAP "ATI Radeon HD 4770" +0x1002 0x94B5 CHIP_RV740|RADEON_NEW_MEMMAP "ATI Radeon HD 4770" 0x1002 0x94C0 CHIP_RV610|RADEON_NEW_MEMMAP "RV610" 0x1002 0x94C1 CHIP_RV610|RADEON_NEW_MEMMAP "Radeon HD 2400 XT" 0x1002 0x94C3 CHIP_RV610|RADEON_NEW_MEMMAP "Radeon HD 2400 Pro" diff --git a/shared-core/r600_cp.c b/shared-core/r600_cp.c index 7525497..6c929d7 100644 --- a/shared-core/r600_cp.c +++ b/shared-core/r600_cp.c @@ -523,11 +523,12 @@ static void r700_cp_load_microcode(drm_radeon_private_t * dev_priv) } RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) { + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) { RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - DRM_INFO("Loading RV730 PFP Microcode\n"); + DRM_INFO("Loading RV730/RV740 PFP Microcode\n"); for (i = 0; i < R700_PFP_UCODE_SIZE; i++) { RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); } @@ -535,7 +536,7 @@ static void r700_cp_load_microcode(drm_radeon_private_t * dev_priv) RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - DRM_INFO("Loading RV730 CP Microcode\n"); + DRM_INFO("Loading RV730/RV740 CP Microcode\n"); for (i = 0; i < R700_PM4_UCODE_SIZE; i++) { RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); } @@ -1367,6 +1368,11 @@ static void r700_gfx_init(struct drm_device * dev, dev_priv->r700_sc_prim_fifo_size = 0xf9; dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; + + if (dev_priv->r600_sx_max_export_pos_size > 16) { + dev_priv->r600_sx_max_export_pos_size -= 16; + dev_priv->r600_sx_max_export_smx_size += 16; + } break; case CHIP_RV710: dev_priv->r600_max_pipes = 2; @@ -1388,6 +1394,31 @@ static void r700_gfx_init(struct drm_device * dev, dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; break; + case CHIP_RV740: + dev_priv->r600_max_pipes = 4; + dev_priv->r600_max_tile_pipes = 4; + dev_priv->r600_max_simds = 8; + dev_priv->r600_max_backends = 4; + dev_priv->r600_max_gprs = 256; + dev_priv->r600_max_threads = 248; + dev_priv->r600_max_stack_entries = 512; + dev_priv->r600_max_hw_contexts = 8; + dev_priv->r600_max_gs_threads = 16 * 2; + dev_priv->r600_sx_max_export_size = 256; + dev_priv->r600_sx_max_export_pos_size = 32; + dev_priv->r600_sx_max_export_smx_size = 224; + dev_priv->r600_sq_num_cf_insts = 2; + + dev_priv->r700_sx_num_of_sets = 7; + dev_priv->r700_sc_prim_fifo_size = 0x100; + dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; + dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; + + if (dev_priv->r600_sx_max_export_pos_size > 16) { + dev_priv->r600_sx_max_export_pos_size -= 16; + dev_priv->r600_sx_max_export_smx_size += 16; + } + break; default: break; } @@ -1536,6 +1567,7 @@ static void r700_gfx_init(struct drm_device * dev, break; case CHIP_RV730: case CHIP_RV710: + case CHIP_RV740: default: sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); break; @@ -1612,6 +1644,7 @@ static void r700_gfx_init(struct drm_device * dev, switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_RV770: case CHIP_RV730: + case CHIP_RV740: gs_prim_buffer_depth = 384; break; case CHIP_RV710: diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 7ee30b1..e0a3e4d 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -146,6 +146,7 @@ enum radeon_family { CHIP_RV770, CHIP_RV730, CHIP_RV710, + CHIP_RV740, CHIP_LAST, };