diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c index dba197e..601e123 100644 --- a/src/radeon_commonfuncs.c +++ b/src/radeon_commonfuncs.c @@ -222,7 +222,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) if (info->accel_state->has_tcl) { /* exa mask/Xv bicubic shader program */ BEGIN_ACCEL(13); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0)); /* PVS inst 0 */ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | @@ -313,7 +313,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) BEGIN_ACCEL(9); /* exa no mask instruction */ - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(3)); /* PVS inst 0 */ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | @@ -375,7 +375,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn) /* Xv shader program */ BEGIN_ACCEL(9); - OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(5)); OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, (R300_PVS_DST_OPCODE(R300_VE_ADD) | diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c index 97199ae..72a32a8 100644 --- a/src/radeon_exa_render.c +++ b/src/radeon_exa_render.c @@ -1042,6 +1042,9 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, */ txformat0 |= R300_TXPITCH_EN; + if (pPict->transform != 0) + txformat0 |= R300_TXPROJECTED; + info->accel_state->texW[unit] = w; info->accel_state->texH[unit] = h; @@ -1054,7 +1057,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix, txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); else txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); - + txfilter |= (unit << R300_TX_ID_SHIFT); switch (pPict->filter) { @@ -1183,11 +1186,14 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, uint32_t dst_format, dst_offset, dst_pitch; uint32_t txenable, colorpitch; uint32_t blendcntl; - int pixel_shift; + int pixel_shift, j; ACCEL_PREAMBLE(); TRACE; + if (pMask) + return FALSE; + if (!info->accel_state->XInited3D) RADEONInit3DEngine(pScrn); @@ -1232,6 +1238,257 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, RADEON_SWITCH_TO_3D(); + BEGIN_ACCEL(1); + if (IS_R300_3D) + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_CONST_INDEX(0)); + else + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R500_PVS_VECTOR_CONST_INDEX(0)); + FINISH_ACCEL(); + + BEGIN_ACCEL(1); + + if (info->accel_state->is_transform[0]) { + BEGIN_ACCEL(12); + for (j = 0; j < 3; j++) { + ErrorF("matrix[%d][0] = %f\n", j, xFixedToFloat(info->accel_state->transform[0]->matrix[j][0])); + ErrorF("matrix[%d][1] = %f\n", j, xFixedToFloat(info->accel_state->transform[0]->matrix[j][1])); + ErrorF("matrix[%d][2] = %f\n", j, xFixedToFloat(info->accel_state->transform[0]->matrix[j][2])); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(info->accel_state->transform[0]->matrix[j][0]))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(info->accel_state->transform[0]->matrix[j][1]))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(0.0)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(info->accel_state->transform[0]->matrix[j][2]))); + } + FINISH_ACCEL(); + } + if (info->accel_state->is_transform[1]) { + BEGIN_ACCEL(12); + for (j = 0; j < 3; j++) { + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(info->accel_state->transform[1]->matrix[j][0]))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(info->accel_state->transform[1]->matrix[j][1]))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(0.0)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, F_TO_DW(xFixedToFloat(info->accel_state->transform[1]->matrix[j][2]))); + } + FINISH_ACCEL(); + } + BEGIN_ACCEL(1); + OUT_ACCEL_REG(R300_VAP_VS_CONST_CNTL, (R300_PVS_CONST_BASE_OFFSET(0) | + R300_PVS_MAX_CONST_ADDR(17))); + FINISH_ACCEL(); + +#if 1 + /* pre-load the vertex shaders */ + if (info->accel_state->has_tcl) { + /* exa no mask instruction */ + /* PVS inst 0 */ + if (info->accel_state->is_transform[0]) + BEGIN_ACCEL(17); + else + BEGIN_ACCEL(9); + + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(3)); + + // X, Y + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_ADD) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(0) | + R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | + R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + + /* PVS inst - tex coords */ + if (info->accel_state->is_transform[0]) { + // S + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(1) | + R300_PVS_DST_WE_X)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | + R300_PVS_SRC_OFFSET(0) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + // T + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(1) | + R300_PVS_DST_WE_Y)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | + R300_PVS_SRC_OFFSET(4) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + // Q + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(1) | + R300_PVS_DST_WE_W)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | + R300_PVS_SRC_OFFSET(7) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + + } else { + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_DST_OPCODE(R300_VE_ADD) | + R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | + R300_PVS_DST_OFFSET(1) | + R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | + R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, + (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | + R300_PVS_SRC_OFFSET(6) | + R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | + R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); + } + FINISH_ACCEL(); + } + + BEGIN_ACCEL(4); + if (info->accel_state->is_transform[0]) { + /* rasterizer source table + * R300_RS_TEX_PTR is the offset into the input RS stream + * 0,1,3 are tex0 + * 4,5,7 are tex1 + */ + OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (3 << R500_RS_IP_TEX_PTR_Q_SHIFT))); + + OUT_ACCEL_REG(R500_RS_IP_1, ((4 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (5 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (7 << R500_RS_IP_TEX_PTR_Q_SHIFT))); + /* src tex */ + /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry + * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data + */ + OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | + R500_RS_INST_TEX_CN_WRITE | + (0 << R500_RS_INST_TEX_ADDR_SHIFT))); + /* mask tex */ + OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | + R500_RS_INST_TEX_CN_WRITE | + (1 << R500_RS_INST_TEX_ADDR_SHIFT))); + } else { + /* rasterizer source table + * R300_RS_TEX_PTR is the offset into the input RS stream + * 0,1 are tex0 + * 2,3 are tex1 + */ + OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); + + OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); + /* src tex */ + /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry + * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data + */ + OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | + R500_RS_INST_TEX_CN_WRITE | + (0 << R500_RS_INST_TEX_ADDR_SHIFT))); + /* mask tex */ + OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | + R500_RS_INST_TEX_CN_WRITE | + (1 << R500_RS_INST_TEX_ADDR_SHIFT))); + } + FINISH_ACCEL(); + +#endif /* setup the VAP */ if (info->accel_state->has_tcl) { if (pMask) @@ -1288,8 +1545,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, /* load the vertex shader * We pre-load vertex programs in RADEONInit3DEngine(): - * - exa no mask * - exa mask + * - exa no mask * - Xv * Here we select the offset of the vertex program we want to use */ @@ -1302,12 +1559,21 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); } else { - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, - ((3 << R300_PVS_FIRST_INST_SHIFT) | - (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | - (4 << R300_PVS_LAST_INST_SHIFT))); - OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, - (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); + if (info->accel_state->is_transform[0]) { + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, + ((3 << R300_PVS_FIRST_INST_SHIFT) | + (6 << R300_PVS_XYZW_VALID_INST_SHIFT) | + (6 << R300_PVS_LAST_INST_SHIFT))); + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, + (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); + } else { + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, + ((3 << R300_PVS_FIRST_INST_SHIFT) | + (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | + (4 << R300_PVS_LAST_INST_SHIFT))); + OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, + (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); + } } } @@ -1318,8 +1584,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, ((2 << R300_TEX_0_COMP_CNT_SHIFT) | (2 << R300_TEX_1_COMP_CNT_SHIFT))); else - OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, - (2 << R300_TEX_0_COMP_CNT_SHIFT)); + if (info->accel_state->is_transform[0]) + OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, + (4 << R300_TEX_0_COMP_CNT_SHIFT)); + else + OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, + (2 << R300_TEX_0_COMP_CNT_SHIFT)); OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); OUT_ACCEL_REG(R300_TX_ENABLE, txenable); @@ -1749,10 +2019,16 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture, R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP)); - OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | - R500_TEX_INST_LD | - R500_TEX_SEM_ACQUIRE | - R500_TEX_IGNORE_UNCOVERED)); + if (info->accel_state->is_transform[0]) + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + R500_TEX_INST_PROJ | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); + else + OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | + R500_TEX_INST_LD | + R500_TEX_SEM_ACQUIRE | + R500_TEX_IGNORE_UNCOVERED)); OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | R500_TEX_SRC_S_SWIZ_R | @@ -1935,6 +2211,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, maskBottomRight.x = IntToxFixed(maskX + w); maskBottomRight.y = IntToxFixed(maskY + h); +#if 0 if (info->accel_state->is_transform[0]) { transformPoint(info->accel_state->transform[0], &srcTopLeft); transformPoint(info->accel_state->transform[0], &srcTopRight); @@ -1947,7 +2224,7 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, transformPoint(info->accel_state->transform[1], &maskBottomLeft); transformPoint(info->accel_state->transform[1], &maskBottomRight); } - +#endif if (info->accel_state->has_mask) vtx_count = VTX_COUNT_MASK; else @@ -2025,16 +2302,29 @@ static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst, xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0], xFixedToFloat(maskTopRight.x) / info->accel_state->texW[1], xFixedToFloat(maskTopRight.y) / info->accel_state->texH[1]); } else { - if (info->ChipFamily >= CHIP_FAMILY_R200) { - VTX_OUT((float)dstX, (float)dstY, - xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]); + if (info->accel_state->is_transform[0]) { + if (info->ChipFamily >= CHIP_FAMILY_R200) { + VTX_OUT((float)dstX, (float)dstY, + xFixedToFloat(srcTopLeft.x), xFixedToFloat(srcTopLeft.y)); + } + VTX_OUT((float)dstX, (float)(dstY + h), + xFixedToFloat(srcBottomLeft.x), xFixedToFloat(srcBottomLeft.y)); + VTX_OUT((float)(dstX + w), (float)(dstY + h), + xFixedToFloat(srcBottomRight.x), xFixedToFloat(srcBottomRight.y)); + VTX_OUT((float)(dstX + w), (float)dstY, + xFixedToFloat(srcTopRight.x), xFixedToFloat(srcTopRight.y)); + } else { + if (info->ChipFamily >= CHIP_FAMILY_R200) { + VTX_OUT((float)dstX, (float)dstY, + xFixedToFloat(srcTopLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcTopLeft.y) / info->accel_state->texH[0]); + } + VTX_OUT((float)dstX, (float)(dstY + h), + xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + w), (float)(dstY + h), + xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]); + VTX_OUT((float)(dstX + w), (float)dstY, + xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]); } - VTX_OUT((float)dstX, (float)(dstY + h), - xFixedToFloat(srcBottomLeft.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomLeft.y) / info->accel_state->texH[0]); - VTX_OUT((float)(dstX + w), (float)(dstY + h), - xFixedToFloat(srcBottomRight.x) / info->accel_state->texW[0], xFixedToFloat(srcBottomRight.y) / info->accel_state->texH[0]); - VTX_OUT((float)(dstX + w), (float)dstY, - xFixedToFloat(srcTopRight.x) / info->accel_state->texW[0], xFixedToFloat(srcTopRight.y) / info->accel_state->texH[0]); } if (IS_R300_3D || IS_R500_3D) diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 19f9869..306645e 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -3976,6 +3976,8 @@ # define R300_SUBPIXEL_1_12 (0 << 16) # define R300_SUBPIXEL_1_16 (1 << 16) #define R300_GB_SELECT 0x401c +# define R300_DEPTH_SELECT (1 << 3) +# define R300_W_SELECT (1 << 4) #define R300_GB_ENABLE 0x4008 #define R300_GB_AA_CONFIG 0x4020 #define R400_GB_PIPE_SELECT 0x402c @@ -4140,6 +4142,12 @@ #define R300_VAP_PVS_CODE_CNTL_1 0x22D8 # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 +# define R300_PVS_CODE_START 0 +# define R300_PVS_CONST_START 512 +# define R500_PVS_CONST_START 1024 +# define R300_PVS_VECTOR_INST_INDEX(x) ((x) + R300_PVS_CODE_START) +# define R300_PVS_VECTOR_CONST_INDEX(x) ((x) + R300_PVS_CONST_START) +# define R500_PVS_VECTOR_CONST_INDEX(x) ((x) + R500_PVS_CONST_START) #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 /* PVS instructions */ /* Opcode and dst instruction */ @@ -4258,6 +4266,10 @@ #define R300_PVS_SRC_ADDR_SEL(x) (x << 29) #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) +#define R300_VAP_VS_CONST_CNTL 0x22d4 +# define R300_PVS_CONST_BASE_OFFSET(x) ((x) << 0) +# define R300_PVS_MAX_CONST_ADDR(x) ((x) << 0) + #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc #define R300_VAP_OUT_VTX_FMT_0 0x2090 # define R300_VTX_POS_PRESENT (1 << 0) @@ -5282,9 +5294,6 @@ # define R500_W_SRC_US (0 << 2) # define R500_W_SRC_RAS (1 << 2) -#define R500_GA_US_VECTOR_INDEX 0x4250 -#define R500_GA_US_VECTOR_DATA 0x4254 - #define R500_RS_INST_0 0x4320 #define R500_RS_INST_1 0x4324 # define R500_RS_INST_TEX_ID_SHIFT 0